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Patent # Description
US-7,994,005 High-mobility trench MOSFETs
High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility...
US-7,994,004 Flash memory cell arrays having dual control gates per memory cell charge storage element
A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least...
US-7,994,003 Nonvolatile memory device and method of fabricating the same
A method of fabricating a nonvolatile memory device includes forming a tunnel insulating layer on a semiconductor substrate, forming a charge storage layer on...
US-7,994,002 Method and apparatus for trench and via profile modification
Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the...
US-7,994,001 Trenched power semiconductor structure with schottky diode and fabrication method thereof
A fabrication method of a trenched power semiconductor structure with a schottky diode is provided. Firstly, a drain region is formed in a substrate. Next, at...
US-7,994,000 Semiconductor device and method of manufacturing the same
To provide a semiconductor device having a memory element, and which is manufactured by a simplified manufacturing process. A method of manufacturing a...
US-7,993,999 High-K/metal gate CMOS finFET with improved pFET threshold voltage
A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor...
US-7,993,998 CMOS devices having dual high-mobility channels
A method for forming a semiconductor structure includes providing a semiconductor substrate including a first region and a second region; and forming a first...
US-7,993,997 Poly profile engineering to modulate spacer induced stress for device enhancement
The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a...
US-7,993,995 Metal-gated MOSFET devices having scaled gate stack thickness including gettering species in a buried oxide
Metal-oxide semiconductor field effect transistor (MOSFET) devices having metal gate stacks and techniques for improving performance thereof are provided. In...
US-7,993,994 Method of forming crystallized silicon and method of fabricating thin film transistor and liquid crystal...
A method of crystallizing amorphous silicon comprises forming an amorphous silicon layer on a substrate; forming an insulating layer on the amorphous silicon...
US-7,993,993 Display device, manufacturing method thereof, and television receiver
The present invention discloses a method for manufacturing a display device comprising the steps of forming a first film pattern using a photosensitive material...
US-7,993,992 Semiconductor device and method of fabricating the same
There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is...
US-7,993,991 Manufacturing method of thin film transistor and manufacturing method of display device
A manufacturing method of a thin film transistor and a display device using a small number of masks is provided. A first conductive film, an insulating film, a...
US-7,993,990 Multiple crystallographic orientation semiconductor structures
A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a...
US-7,993,989 Vertical spacer forming and related transistor
Methods include, for example, forming a vertically disposed active region on a substrate; forming a first gate over a portion of the vertically disposed active...
US-7,993,988 Techniques for fabricating a non-planar transistor
Methods for fabricating a non-planar transistor. Fin field effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member)....
US-7,993,987 Surface cleaning using sacrificial getter layer
A method includes providing a substrate including a non-insulative, silicon-including region for silicidation, the substrate including one or more contaminants...
US-7,993,986 Sidewall graphene devices for 3-D electronics
A device is provided that includes a structure having a sidewall surface, a layer of material provided on the sidewall surface, and a device structure provided...
US-7,993,985 Method for forming a semiconductor device with a single-sided buried strap
A method for forming a semiconductor device with a single-sided buried strap is provided. The method includes the steps of providing a substrate with a trench,...
US-7,993,984 Electronic device and manufacturing method
An electronic device including a semiconductor device with a plurality of bump electrodes, a mounting board connected to the semiconductor device, thermally...
US-7,993,983 Method of making a semiconductor chip assembly with chip and encapsulant grinding
A method of making a semiconductor chip assembly includes mechanically attaching a semiconductor chip to a routing line, then forming an encapsulant that covers...
US-7,993,982 Quad flat non-leaded package and manufacturing method thereof
A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound...
US-7,993,981 Electronic device package and method of manufacture
A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite...
US-7,993,980 Lead frame, electronic component including the lead frame, and manufacturing method thereof
A lead frame of the present invention includes: a die pad on which a device is mounted; a first connection terminal which is provided around the die pad, and...
US-7,993,979 Leadless package system having external contacts
A leadless package system includes: providing a chip carrier having indentations defining a pattern for a protrusion for external contact terminals; placing an...
US-7,993,978 Method of manufacturing a semiconductor device and molding die
A method of manufacturing a semiconductor device capable of obtaining high joining force between a heat spreader and resin is provided. The method of...
US-7,993,977 Method of forming molded standoff structures on integrated circuit devices
A method of forming molding standoff structures on integrated circuit devices is disclosed which includes forming a plurality of standoff structures on a...
US-7,993,976 Semiconductor device and method of forming conductive vias with trench in saw street
A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is...
US-7,993,975 Method of manufacturing semiconductor device including mounting and dicing chips
A semiconductor-device manufacturing method includes: forming terminals on a wafer and across each of dicing lines along which the wafer is cut into a plurality...
US-7,993,974 Method for manufacturing a semiconductor device
A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a...
US-7,993,973 Structure combining an IC integrated substrate and a carrier, and method of manufacturing such structure
The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed...
US-7,993,972 Wafer level die integration and method therefor
A method of manufacturing a semiconductor device includes providing a wafer for supporting the semiconductor device. An insulation layer is disposed over a top...
US-7,993,971 Forming a 3-D semiconductor die structure with an intermetallic formation
A method for forming a semiconductor structure includes forming a first contact pad on a first die, wherein the first contact pad comprises a first metal...
US-7,993,970 Semiconductor device and fabrication method thereof
A semiconductor device and a method of manufacturing the same are disclosed. The method is carried out by forming solder pads on a substrate by wet etching,...
US-7,993,969 Method for producing a module with components stacked one above another
The invention relates to a method in which components (101, 102) are provided, movement elements (104) are in each case applied to surfaces of a number of the...
US-7,993,968 Assembling substrates that can form 3-D structures
A system is described that connects the surface of a first substrate to the edge of a second substrate. The surfaces of additional substrates can be placed on...
US-7,993,967 Semiconductor package fabrication method
A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier,...
US-7,993,966 Method for manufacturing silicon carbide semiconductor device having high channel mobility
A silicon carbide semiconductor device having a MOS structure includes: a substrate; a channel area in the substrate; a first impurity area; a second impurity...
US-7,993,965 Process for producing semiconductive porcelain composition/electrode assembly
A semiconductive porcelain composition/electrode assembly which is low in room temperature resistivity of 100 .OMEGA.cm or less and is reduced in change with...
US-7,993,964 Manufacturing method of semiconductor device including active layer of zinc oxide with controlled crystal...
A manufacturing method of a semiconductor device includes forming an oxide semiconductor thin film layer of zinc oxide, wherein at least a portion of the oxide...
US-7,993,963 Phase change layer and method of manufacturing the same and phase change memory device comprising phase change...
Provided are a phase change layer and a method of forming the phase change layer and a phase change memory device including the phase change layer, and methods...
US-7,993,962 I-shaped phase change memory cell
A memory device includes two electrodes, vertically separated and having mutually opposed contact surfaces, between which lies a phase change cell. The phase...
US-7,993,961 Layout structure in semiconductor memory device comprising global word lines, local word lines, global bit...
A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a...
US-7,993,960 Electronic device and method of manufacturing the same
Provided are an electronic device including a bank structure and a method of manufacturing the same. The method of manufacturing the electronic device requires...
US-7,993,959 Methods for producing multiple distinct transistors from a single semiconductor
Provided are methods for producing multiple distinct transistors from a single semiconductor layer, and apparatus incorporating transistors so produced.
US-7,993,958 Organic thin film transistor array panel and manufacturing method thereof
A method of manufacturing a thin film transistor array panel is provided, the method including: forming a gate line on a substrate; forming a gate insulating...
US-7,993,957 Phase change memory cell and manufacturing method thereof using minitrenches
A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin...
US-7,993,956 Poly diode structure for photo diode
An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed...
US-7,993,955 Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass...
The thermal management and method for large scale processing of CIS and/or CIGS based thin film overlaying glass substrates. According to an embodiment, the...
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