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| Patent # | Description |
|---|---|
| US-8,000,159 |
Semiconductor memory device having memory block configuration A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region... |
| US-8,000,158 |
Semiconductor memory device including repair redundancy memory cell arrays A semiconductor memory device includes a plurality of memory cell matrixes each of which contains plural memory cell arrays whose number is lager than 2.sup.n... |
| US-8,000,157 |
RAM macro and timing generating circuit thereof A timing generating circuit generates a control clock (1) and a test clock (2) based on an externally input clock CLK, and outputs the generated clocks to a... |
| US-8,000,156 |
Memory device with propagation circuitry in each sub-array and method
thereof A memory device and method of operating such a device are provided. The memory device has a plurality of sub-arrays arranged to form at least one sub-array... |
| US-8,000,155 |
Non-volatile memory device and method for writing data thereto The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and... |
| US-8,000,154 |
Non-volatile memory device and method of controlling a bulk voltage
thereof A non-volatile memory device comprises a voltage supplier comprising memory cells in which the voltage supplier supplies a positive set voltage to a bulk of a... |
| US-8,000,153 |
Enhanced erase for flash storage device A flash storage device includes flash storage units that are erased in response to a condition or command while allowing the flash storage device to be used... |
| US-8,000,152 |
Charge pump operation in a non-volatile memory device A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial... |
| US-8,000,151 |
Semiconductor memory column decoder device and method Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in... |
| US-8,000,150 |
Method of programming memory device A method of programming a memory device may include applying a program voltage to a memory cell of the memory device and consecutively applying a plurality of... |
| US-8,000,149 |
Non-volatile memory device The present invention relates to a method of operating a non-volatile memory device. In an aspect of the present invention, the method includes performing a... |
| US-8,000,148 |
Methods of operating nonvolatile memory devices Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells,... |
| US-8,000,147 |
Nonvolatile semiconductor memory device A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is... |
| US-8,000,146 |
Applying different body bias to different substrate portions for
non-volatile storage Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an... |
| US-8,000,145 |
Method for programming nand type flash memory Disclosed is a method for programming a flash memory device capable of preventing a threshold voltage distribution of a memory cell from being moved due to a... |
| US-8,000,144 |
Method and system for accessing a flash memory device An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory... |
| US-8,000,143 |
Nonvolatile memory device including circuit formed of thin film
transistors A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense... |
| US-8,000,142 |
Semi-volatile NAND flash memory Semi-volatile NAND flash memory systems, apparatuses, and methods for use are described herein. According to various embodiments, a semi-volatile NAND flash... |
| US-8,000,141 |
Compensation for voltage drifts in analog memory cells A method for data storage includes storing data in a group of analog memory cells by writing respective first storage values into the memory cells. After... |
| US-8,000,140 |
Random access memory with CMOS-compatible nonvolatile storage element Embodiments provide systems, methods, and apparatuses with a plurality of row lines and column lines arranged in a matrix, and at least one memory cell having... |
| US-8,000,139 |
Multiple time programmable (MTP) PMOS floating gate-based non-volatile
memory device for a general purpose CMOS... A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and... |
| US-8,000,138 |
Scaleable memory systems using third dimension memory A non-volatile scalable memory circuit is described, including a bus formed on a substrate that includes active circuitry, metallization layers, and a plurality... |
| US-8,000,137 |
Nonvolatile semiconductor memory device and usage method thereof A nonvolatile semiconductor memory device includes a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors... |
| US-8,000,136 |
Non-volatile memory with both single and multiple level cells Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled... |
| US-8,000,135 |
Estimation of memory cell read thresholds by sampling inside programming
level distribution intervals A method for data storage includes storing data in a group of analog memory cells by writing into the memory cells in the group respective storage values, which... |
| US-8,000,134 |
Off-die charge pump that supplies multiple flash devices A system and method for storing data uses multiple flash memory dies. Each flash memory die includes multiple flash memory cells. A charge pump is adapted to... |
| US-8,000,133 |
Thin film magnetic memory device capable of conducting stable data read
and write operations A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free... |
| US-8,000,132 |
Method for efficiently driving a phase change memory device A method for efficiently driving a phase change memory device is presented that includes the operational procedures of writing, reading, comparing and changing.... |
| US-8,000,131 |
Non-volatile field programmable gate array A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to... |
| US-8,000,130 |
Semiconductor memory device with sense circuit connected to sense node
coupled to bit line A semiconductor memory device comprises a word line; a bit line crossing the word line; a memory cell connected to intersection of the word line and the bit... |
| US-8,000,129 |
Field-emitter-based memory array with phase-change storage devices Embodiments of the present invention include systems and methods for three-terminal field-emitter triode devices, and memory arrays utilizing the same. In other... |
| US-8,000,128 |
Structures for resistive random access memory cells A resistive random access memory (RRAM) cell that includes a first electrode having a lower portion, a continuous side portion and an upper portion, the lower... |
| US-8,000,127 |
Method for resetting a resistive change memory element A method of resetting a resistive change memory element is disclosed. The method comprises performing a series of programming operations--for example, a... |
| US-8,000,126 |
Semiconductor device with recording layer containing indium, germanium,
antimony and tellurium A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on... |
| US-8,000,125 |
Method of programming multi-layer chalcogenide devices A method of programming a multi-layer chalcogenide electronic device. The device includes an active region in electrical communication with two terminals, where... |
| US-8,000,124 |
Symmetric blocking transient voltage suppressor (TVS) using bipolar
transistor base snatch A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically... |
| US-8,000,123 |
Semiconductor memory device of open bit line type There is provided a semiconductor memory device that includes: a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a... |
| US-8,000,122 |
Media player with non-volatile memory A media player is provided that includes a processor configured to execute a media player program, a non-volatile memory electrically coupled with the... |
| US-8,000,121 |
Solid state drive with non-volatile memory for a media device A media device is provided that includes a processor configured to execute a media device program, a non-volatile memory electrically coupled with the... |
| US-8,000,120 |
Read and match circuit for low-voltage content addressable memory A read, write, and match circuit for a low-voltage content addressable memory. A write circuit inputs signals for storing data in the memory cells, a read... |
| US-8,000,119 |
Switching mode power supply and method of operation In one embodiment, an SMPS includes a rectifier for generating an input DC voltage from an input AC voltage. A switching transistor is coupled to a primary coil... |
| US-8,000,118 |
Method and system for delivering a controlled voltage In general, in one aspect, the invention relates to a method for delivering a controlled voltage. The method involves, during a first electric pulse delivered... |
| US-8,000,117 |
Buck boost function based on a capacitor bootstrap input buck converter A buck boost voltage converter circuit has a capacitor pump circuit for boosting an input voltage in a first mode of operation when an input voltage is below a... |
| US-8,000,116 |
Output protection circuit of a power converter An output protection circuit used for a power converter having an operational amplifier, a diode, a number of voltage-dividing resistors, and a switch tube. In... |
| US-8,000,115 |
Flyback power supply with forced primary regulation A flyback converter controller with forced primary regulation is disclosed. An example flyback converter controller includes a secondary control circuit to be... |
| US-8,000,114 |
Method and apparatus for a control circuit with multiple operating modes An apparatus of regulating a power converter with multiple operating modes includes a switch coupled to an energy transfer element coupled between an input and... |
| US-8,000,113 |
Efficient power regulation for class-E amplifiers A power converter device and method are provided. The power converter device includes an input power source and an input inductor configured for coupling a... |
| US-8,000,112 |
Active snubber for transition mode power converter A transition mode power converter having an active snubber the operation of which is controlled using an auxiliary winding on the transformer of the power... |
| US-8,000,111 |
Electronic device structure An electronic device structure includes an upper case, a lower case, a main board, a suspending member, and a fixing member. The upper case and the lower case... |
| US-8,000,110 |
Connector hold down and method A device may include a connector receptacle coupled to a motherboard; a connector hold-down disposed adjacent to the connector receptacle; and/or a connector... |
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