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| Patent # | Description |
|---|---|
| US-8,006,115 |
Central processing unit with multiple clock zones and operating method One embodiment of the invention comprises, in each clock zone of a central processing unit, at least one sensor that generates a power signal indicative of a... |
| US-8,006,114 |
Software programmable timing architecture An apparatus for generating a digital signal pattern may comprises a memory, a program sequencer, first and second circuits, and an event execution unit. The... |
| US-8,006,113 |
System and method for controlling voltage level and clock frequency
supplied to a system A system that includes at least one component adapted to execute at least one application, characterized by including a controller adapted to receive at least... |
| US-8,006,112 |
System and method for managing blades after a power supply unit failure Systems and methods for managing blades in the event of a power supply unit failure are disclosed. A method may include determining whether a reduced power... |
| US-8,006,111 |
Intelligent file system based power management for shared storage that
migrates groups of files based on... A file server includes active storage containing frequently accessed files, and active/inactive disk drives for containing infrequently accessed files. Groups... |
| US-8,006,110 |
Method and apparatus for keeping a virtual private network session active
on a portable computer system... An apparatus for keeping a VPN session alive on a portable computer system such as a laptop computer includes a processor that executes instructions that... |
| US-8,006,109 |
Information processing apparatus and power supply control method According to one embodiment, an information processing apparatus includes a housing, a power supply incorporated in the housing, a conversion unit which... |
| US-8,006,108 |
Dynamic selection of group and device power limits A variable group power limit is enforced to limit the net power consumption of a group of devices in a computer system, and a variable device power limit... |
| US-8,006,107 |
Method for remote power control and the circuit thereof The present invention provides a remote control system for a power supply, comprising: a display data channel (DDC); a first control circuit electrically... |
| US-8,006,106 |
Method and system for flexibly supplying power to a high-end graphics card
using an off-card voltage converter... A method and system for flexibly supplying power to a high-end graphics card is described. The graphics system includes the high-end graphics card and also a... |
| US-8,006,105 |
AC-powered in-wall computing device with power-line networking
capabilities Apparatus and systems provide processing capabilities and power-line networking capabilities. An in-wall computing device has a power connector for receiving an... |
| US-8,006,104 |
Ethernet powered computing device and system Apparatus and systems provide processing capabilities while utilizing power received via an Ethernet. A computing device has an Ethernet connector for receiving... |
| US-8,006,103 |
TPM device for multi-processor systems In one embodiment, a computer system comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one... |
| US-8,006,102 |
Method and apparatus for transmitting content data and recording and/or
reproducing apparatus A data transmission method and apparatus for transmitting data, such as encrypted content data. A device that is to be a destination of transmission is... |
| US-8,006,101 |
Radio transceiver or other encryption device having secure
tamper-detection module An encryption device includes a system processor having a first key for encrypting information. The system processor periodically generates random data strings... |
| US-8,006,100 |
Enhancing trusted platform module performance A computer system comprises a system trust module for taking measurements for platform specific firmware during a system boot and a trust subsystem comprising a... |
| US-8,006,099 |
Security management method, program, and information device In a state in which a fingerprint authentication mode is set, a fingerprint authentication unit authenticates a fingerprint input in accordance with an input... |
| US-8,006,098 |
Integrating legacy application/data access with single sign-on in a
distributed computing environment The present invention provides methods, systems, computer program products, and methods of doing business whereby legacy host application/system access is... |
| US-8,006,097 |
Password generation using genre selection Presently disclosed herein are a method, system, and computer-readable medium for managing a user-defined genre-based password. In one embodiment, the method... |
| US-8,006,096 |
Information processing apparatus There is described an information processing apparatus, which makes it possible to discriminate the injustice inputting operation from the input error simply... |
| US-8,006,095 |
Configurable signature for authenticating data or program code System and method for authenticating data or program code via a configurable signature. Configuration information is retrieved from a protected first memory,... |
| US-8,006,094 |
Trustworthy timestamps and certifiable clocks using logs linked by
cryptographic hashes A method and apparatus for creating and/or using trustworthy timestamps and certifiable clocks using logs linked by cryptographic hashes. In one embodiment, the... |
| US-8,006,093 |
Instant messaging private tags Systems for instant messaging private tags preferably comprise a parser for parsing an instant message for sensitive data and an encryption engine for... |
| US-8,006,092 |
Digital watermarks for checking authenticity of printed objects The invention provides methods for embedding digital watermarks for authentication of printed objects, and corresponding methods for authenticating these... |
| US-8,006,091 |
Method and apparatus to provide failover capability of cached secure
sessions A method, apparatus and computer program product for providing failover capability of cached secure sessions is presented. A cached secure session involving a... |
| US-8,006,090 |
System and method for combining user and platform authentication in
negotiated channel security protocols A network security handshake exchange for combining user and platform authentication. The security handshake exchange performs operations on a pre-master secret... |
| US-8,006,089 |
Multiple PANA sessions The preferred embodiments provide a novel system and method for reducing authentication delay of a mobile node with a network that includes: employing two EAP... |
| US-8,006,088 |
Methods and systems for network-based management of application security To control privileges and access to resources on a per-process basis, an administrator creates a rule that may be applied to modify a process's token. The rule... |
| US-8,006,087 |
Systems and methods for secure transaction management and electronic
rights protection The present invention provides systems and methods for secure transaction management and electronic rights protection. Electronic appliances such as computers... |
| US-8,006,086 |
Revocation of cryptographic digital certificates A computer system (110) provides validity status proofs each of which proves the validity or invalidity of a set (F) of one or more digital certificates (104).... |
| US-8,006,085 |
License management system and method A license-management system and method is provided. A method of issuing a proxy certificate includes transmitting a proxy-certificate-issuance-request message... |
| US-8,006,084 |
Apparatus and method for managing plurality of certificates An apparatus and method for managing a plurality of certificates are provided. The apparatus for managing a plurality of certificates includes a plurality of... |
| US-8,006,083 |
Image forming apparatus, authentication method, and recording medium An image forming apparatus is configured to receive user authentication information and perform image formation based on an image formation request and is... |
| US-8,006,082 |
Dynamically reconfiguring platform settings In one embodiment, a system may receive a pattern from an analysis engine, where the pattern includes information regarding a corrective action to be taken on a... |
| US-8,006,081 |
Computer program product for generic and flexible collection of a hardware
data image A method of processing data is proposed. In response to determining that a reconfiguration of a data processing system has occurred, one or more system items... |
| US-8,006,080 |
Apparatus, method, computer program and recording medium for processing
information An information processing apparatus for transitioning from an operating state for performing a process in accordance with an application program to a pause... |
| US-8,006,079 |
System and method for fast restart of a guest operating system in a
virtual machine environment The present invention provides a system and method for fast restart of a guest operating system executing on a virtual machine operating system in a virtual... |
| US-8,006,078 |
Central processing unit having branch instruction verification unit for
secure program execution Provided are a central processing unit (CPU) and method for executing a branch instruction of a CPU, which can protect user's data by preventing an error due to... |
| US-8,006,077 |
Thread migration control based on prediction of migration overhead A processing system features a first processing core to operate in a first node, a second processing core to operate in a second node, and random access memory... |
| US-8,006,076 |
Processor and program execution method capable of efficient program
execution A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the... |
| US-8,006,075 |
Dynamically allocated store queue for a multithreaded processor Systems and methods for storage of writes to memory corresponding to multiple threads. A processor comprises a store queue, wherein the queue dynamically... |
| US-8,006,074 |
Methods and apparatus for executing extended custom instructions Methods and apparatus are provided for efficiently executing extended custom instructions on a programmable chip. Components of a processor core such as... |
| US-8,006,073 |
Simultaneous speculative threading light mode A system and method for management of resource allocation of threads for efficient execution of instructions. Prior to dispatching decoded instructions of a... |
| US-8,006,072 |
Reducing data hazards in pipelined processors to provide high processor
utilization A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of... |
| US-8,006,071 |
Processors operable to allow flexible instruction alignment Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of... |
| US-8,006,070 |
Method and apparatus for inhibiting fetch throttling when a processor
encounters a low confidence branch... An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue... |
| US-8,006,069 |
Inter-processor communication method Inter-processor communication systems and methods that define within the instruction set of the microprocessor a command for directing the microprocessor to... |
| US-8,006,068 |
Processor access to data cache with fixed or low variable latency via
instructions to an auxiliary processing unit Access to data storage is described. A general-purpose processor and an auxiliary processing unit (APU) interface coupled to the general-purpose processor are... |
| US-8,006,067 |
Flexible results pipeline for processing element A flexible results pipeline for a processing element of a parallel processor is described. A plurality of result registers are selectively connected to each... |
| US-8,006,066 |
Method and circuit configuration for transmitting data between a processor
and a hardware arithmetic-logic unit A method for transmitting data of a plurality of data types between a digital processor and a hardware arithmetic-logic unit with at least one associated table... |
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