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Patent # Description
US-8,015,466 Adapting scan-BIST architectures for low power operation
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
US-8,015,465 Scan control method and device
A scan control method of a circuit device including setting information indicating scan mode in a register is provided. The scan control method includes cutting...
US-8,015,464 Segmented scan paths with cache bit memory inputs
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and...
US-8,015,463 IC with TAP, DIO interface, SIPE, and PISO circuits
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
US-8,015,462 Test circuit
A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first...
US-8,015,461 Decompressors for low power decompression of test patterns
Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of...
US-8,015,460 Test mode for parallel load of address dependent data to enable loading of desired data backgrounds
One or more embodiments of the invention enable a memory device to load its memory array with desired background data, such as to reduce total test time and...
US-8,015,459 Semiconductor memory device and method of performing a memory operation
A semiconductor memory device and method directed to performing a memory operation in a semiconductor memory device are provided. The method includes receiving...
US-8,015,458 Fault isolation in interconnect systems
A loopback connector for a system can include a connector arrangement connectable to connector of a system component and/or a cable. The loopback connector can...
US-8,015,457 Redundancy circuit and semiconductor memory device
Disclosed is a circuit for deciding whether or not a plural number of redundancy ROM circuits have been programmed in a preset order, with regards to addresses....
US-8,015,456 Network fault manager for maintaining alarm conditions
The network fault manager described herein may generate an alarm data table having various columns and rows respectively corresponding to different alarm data...
US-8,015,455 Self-service terminal for making deposits and for permitting withdrawals
Apparatus and methods for initiating remediation of a condition in an electronic self-service device. The apparatus and methods may involve a receiver module...
US-8,015,454 Computer systems and methods for predictive performance management of data transactions
Systems and methods are disclosed for monitoring and managing data transactions, such as SQL transactions. In certain examples, a management subsystem generates...
US-8,015,453 System and method for correcting errors in downloading web pages
A system and method for correcting errors in downloading web pages provides a historic error resolving procedure and a common error resolving procedure. The...
US-8,015,452 Flexible bus architecture for monitoring and control of battery pack
The present invention provides a control system which is used for a stacked battery of a plurality of battery packs. Each battery pack has a plurality of...
US-8,015,451 Controlling an unreliable data transfer in a data channel
Controlling an unreliable data transfer in a data channel from a transmitting unit to a receiving unit. A bypass mode or a buffer mode is activated depending on...
US-8,015,450 Systems and methods for detecting and automatically installing missing software components
Computer-implemented methods and systems for detecting and automatically installing missing software components are disclosed. In one example, an exemplary...
US-8,015,449 Computer, and method for error-detecting and booting of BIOS thereof
A computer has a first BIOS unit, a second BIOS unit, a bus, a detecting unit, and a first delay unit. The detecting unit is connected to the bus, the first...
US-8,015,448 System and method for conducting BIST operations
A storage controller including a first controller. The first controller includes a memory module, a test access port controller, the test access port controller...
US-8,015,447 Processor debugging apparatus and processor debugging method
A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor...
US-8,015,446 User interface for a remote control application
A hand-held electronic device having a remote control application user interface that functions to displays operational mode information to a user. The...
US-8,015,445 Fault location device, communication device, and fault location method
A fault location device detects a communication device connected to a broken communication line from among communication devices that carry out communications...
US-8,015,444 Protection of non-volatile memory component against data corruption due to physical shock
A device, a computer readable medium, and a method are provided. The device includes, but is not limited to, a sensor, a processor, a non-volatile memory, and a...
US-8,015,443 Reproduction test service apparatus for medical systems, maintenance support information management apparatus,...
In order to reproduce the past operations of a medical system, a reproduction test service apparatus stores a plurality of past log files directly or indirectly...
US-8,015,442 Anomaly notification control in disk array
In a storage device incorporating a plurality of kinds of disk drives with different interfaces, the controller performs sparing on a disk drive, whose errors...
US-8,015,441 Verification of computer backup data
A backup method for a computer system network avoids generating hashes from data that may be inaccurate due to network errors affords verification of source...
US-8,015,440 Apparatus, system, and method for data storage using progressive raid
An apparatus, system, and method are disclosed for data storage with progressive redundant array of independent drives ("RAID"). A storage request receiver...
US-8,015,439 Method for handling more than a maximum number of supported drives in a raid configuration
The present invention is a method for handling disk drives in a Redundant Array of Inexpensive Disks (RAID) configuration. The method may include detecting a...
US-8,015,438 Memory circuit
The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective...
US-8,015,437 Restoring data to a distributed storage node
A method is disclosed for operating a data storage system having one or more network interfaces and a plurality of data storage nodes configured to provide...
US-8,015,436 Resilient data storage in the presence of replication faults and rolling disasters
A method for data protection includes, in a first operational mode, sending data items for storage in a primary storage device and in a secondary storage...
US-8,015,435 Data writing method
According to an aspect of an embodiment, a method for controlling a controller connected to a plurality of storage units storing data, the controller including...
US-8,015,434 Management apparatus, storage system, and storage apparatus management method
There is provided a management apparatus of a storage apparatus. The management apparatus includes an acquisition determination section that determines whether...
US-8,015,433 Disk drive with nonvolatile memory for storage of failure-related data
A disk drive that includes nonvolatile memory monitors the drive's reliability-related parameters to detect real or potential failure events, and records...
US-8,015,432 Method and apparatus for providing computer failover to a virtualized environment
A method and apparatus for providing failover to a virtualized environment. The method and apparatus comprise a standby node having a virtualized environment...
US-8,015,431 Cluster system and failover method for cluster system
Provided is a failover method for a cluster system for realizing smooth failover of the guest OS's, even when there are many guest OS's, while reducing...
US-8,015,430 Using asset dependencies to identify the recovery set and optionally automate and/or optimize the recovery
In one embodiment, a computer accessible medium stores a plurality of instructions including instructions which, when executed: track dependencies among a...
US-8,015,429 Clock and data recovery (CDR) method and apparatus
Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a...
US-8,015,428 Processing device and clock control method
A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal...
US-8,015,427 System and method for prioritization of clock rates in a multi-core processor
A system and method for prioritization of clock rates in a multi-core processor is provided. Instruction arrival rates are measured during a time interval...
US-8,015,426 System and method for providing voltage power gating
A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a...
US-8,015,425 Power reduction techniques for components in integrated circuits
Optimizing the power used in an integrated circuit. A circuit-level transformation/permutation reduces the power consumed by multipliers or other components in...
US-8,015,424 Portable information processing apparatus and method of the same
The present invention relates to a portable information apparatus which can realize electrical power for a longer period of time. Under the condition that the...
US-8,015,423 Temporally normalized processor utilization
A temporally normalized processor utilization trace is generated.
US-8,015,421 Power saving apparatus and method for a portable appliance
A power saving apparatus for a portable appliance includes a sensor unit and a control unit. When the portable appliance is raised up, the sensor unit presents...
US-8,015,420 System and method for power management of a storage enclosure
A system and method for power management of storage enclosures are disclosed. A system may include a storage enclosure and a host communicatively coupled to the...
US-8,015,419 Method and apparatus for soft start power gating with automatic voltage level detection
A method and apparatus for selectively charging a secondary voltage rail includes selectively and partially charging a secondary voltage rail using at least one...
US-8,015,418 Method and apparatus for improved information transactions
Methods and systems for analyzing an image, such as a newspaper or magazine pager or the like including text by mapping the image to determine regions of text...
US-8,015,417 Remote access system, gateway, client device, program, and storage medium
Disclosed is a secure remote access system for improving convenience of a user by utilizing a storage device including an anti-tampering device as a user...
US-8,015,416 Memory information protection system and methods
An information processing apparatus causes an encryption key data generating section to generate key data stored in a semiconductor memory by using encryption...
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