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Patent # Description
US-8,020,064 Decoding apparatus and method
A decoding apparatus and method are described. The decoder includes N successive decoder groups numbered 1 to N arranged in series. Each decoder group includes...
US-8,020,063 High rate, long block length, low density parity check encoder
There is provided a parity check encoder (100) comprising a data memory (PPDM) configured for storing input data, a calculation/parity result data store...
US-8,020,062 Apparatus and method of encoding/decoding block low density parity check codes in a communication system
An apparatus and method of encoding a block Low Density Parity Check (LDPC) code in a signal transmission apparatus is disclosed. The method includes generating...
US-8,020,061 Method for detecting errors and supporting reconfiguration decisions in mobile radio networks comprising...
A respective agent platform in network elements and producer-specific agents that are installed directly on platform or by way of agent proxies of agent...
US-8,020,060 Method of arranging data in a multi-level cell memory device
A method of storing data includes storing a first portion of data in bit positions of a non-volatile memory having a first probability of error; storing a...
US-8,020,059 Tap and control with data I/O, TMS, TDI, and TDO
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
US-8,020,058 Multi-chip digital system having a plurality of controllers with self-identifying signal
The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality...
US-8,020,057 Comparator circuitry connected to input and output of tristate buffer
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response...
US-8,020,056 Memory channel with bit lane fail-over
Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having...
US-8,020,055 Method and apparatus for testing the connectivity of a flash memory chip
In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory...
US-8,020,054 Test apparatus and test method
A test apparatus provided in common for a plurality of memories under test, comprising an address generating section that sequentially generates addresses to be...
US-8,020,053 On-line memory testing
A method of testing on-line and spare memory is disclosed. Such memory may currently store in-use data at some addresses. The testing is initiated upon an...
US-8,020,052 Fault analysis result generating system and method
A fault analysis result generating system includes an extracting unit, a converting unit, a determining unit, and a result generating unit. The system extracts...
US-8,020,051 Message handling in a service-oriented architecture
A service call to a backend system is initiated by a user interface in a service-oriented architecture. Thereafter, a service answer is received from the...
US-8,020,050 Validation of computer interconnects
A method of validating multi-cluster computer interconnects includes calculating a cable interconnect table associated with the multi-cluster computer, and...
US-8,020,049 Detection of and recovery from an electrical fast transient/burst (EFT/B) on a universal serial bus (USB) device
An Electrical Fast Transient/Burst (EFT/B) detection and recovery system for a Universal Serial Bus (USB) device. The system includes a USB core and a burst...
US-8,020,048 Power-on self test program management apparatus and its management method and program
A POST management apparatus for managing a POST of an SB in a partition which operates in units of an OS using the CPU of the SB as a resource accesses the...
US-8,020,047 Method and apparatus for managing storage of data
In a method and apparatus for storage of data, data is stored. The stored data is checked, for example periodically and/or on data access, for development of a...
US-8,020,046 Transaction log management
A transaction processing system comprising a transaction log, a log management policy, a profile and a log manager, and method for managing the transaction log...
US-8,020,045 Root cause analysis method, apparatus, and program for IT apparatuses from which event information is not obtained
In the system management server, an information processing apparatus that is an event-information acquisition target is registered as a monitored apparatus in...
US-8,020,044 Distributed batch runner
Method and systems for allocating test scripts across a plurality of test machines is described. A set of test scripts may be maintained where the set of test...
US-8,020,043 Field failure data collection
The operation of a powered device is monitored to detect a failure condition, the powered device connected to power sourcing equipment by a communications...
US-8,020,042 System and method for supporting compensation work
A method for supporting compensation work comprises the steps of associating a data structure with a compensation function, and associating the data structure...
US-8,020,041 Method and computer system for making a computer have high availability
A method and a computer system for making a computer achieve high availability. The method includes running a host virtual machine on a host virtual machine...
US-8,020,040 Information processing apparatus for handling errors
In the event of occurrence of an error in a memory in an information processor, a first processor that is one of a number of processors executes an error...
US-8,020,039 Recovering from errors in streaming DSP applications
A data processing system is provided in which processing circuitry performs at least one of a series of data processing operations in dependence upon a set of...
US-8,020,038 System and method for adjusting operating points of a processor based on detected processor errors
A processor comprises a processor core and a controller. The processor core has an execution unit configured to execute instructions and to attempt to perform...
US-8,020,037 Creation of a test bed for testing failover and failback operations
Example embodiments provide various techniques for creating a test bed for testing failover and failback operations. In an example, data is stored on a primary...
US-8,020,036 Virtual disk drive system and method
A disk drive system and method capable of dynamically allocating data is provided. The disk drive system may include a RAID subsystem having a pool of storage,...
US-8,020,035 Expander circuit for a solid state persistent storage device that provides a plurality of interfaces to...
A system includes a solid state persistent storage device, and a plurality of storage controllers to manage access of the solid state persistent storage device....
US-8,020,034 Dependency filter object
A dependency filter object for use in a server cluster is described. In an implementation, a method includes bringing online one or more resource objects...
US-8,020,033 Logical entity fault isolation in network systems management
Various embodiments include one or more of systems, methods, and software to provide a status of a logical entity between entity models in network management...
US-8,020,032 Method for providing deferred maintenance on storage subsystems
A set of disks in a plurality of disk arrays are configured to have one or more spare partitions. Upon detecting a faulty disk in a faulty array, the method...
US-8,020,031 System and method for customizing a SCSI error response received from a SCSI target in a storage network...
A system and method for customizing a SCSI error response received from a SCSI target in a storage network environment is disclosed. In a method for customizing...
US-8,020,030 Counter-invasive software system and method
A method and apparatus for detecting, curing and remedying invasive software installation inadvertently, negligently, or intentionally marketed by a vendor. A...
US-8,020,029 Method and apparatus for rendering game assets in distributed systems
The invention includes a method and apparatus for attempting to synchronize delivery of information at a plurality of receiving systems. The method includes...
US-8,020,028 Application management system for mobile devices
An application management system identifies a mobile device for use in a vehicle, home, or place of business, each of which includes a processor and is designed...
US-8,020,027 Timing control in a specialized processing block
The tension between f.sub.max and T.sub.co in a specialized processing block of a programmable integrated circuit device can be reduced by providing variable...
US-8,020,026 Phase-aligning corrected and uncorrected clocks
The present invention relates to providing a system clock signal that is based on either a first clock signal that is capable of being frequency-corrected or a...
US-8,020,025 Power saving scheduler for timed events
The disclosed system and methods include a power saving scheduler that maintains timed events in an event table. Each timed event has an associated tolerance...
US-8,020,024 Method for preventing erroneous resetting of electronic device due to electrostatic discharge
An exemplary method for preventing an electronic device from erroneously resetting due to electrostatic discharge (ESD) involves an electronic device that...
US-8,020,023 Systems and methods for synchronizing operations among a plurality of independently clocked digital data...
Exemplary systems and methods include a distribution device that maintains a clock rate and distributes a series of tasks to a group of execution devices. Each...
US-8,020,022 Delay time control of memory controller
A memory control circuit has a write leveling function and controls read/write operations by supplying a clock signal to a plurality of memories through a clock...
US-8,020,021 Two global precise times for synchronization
Method of controlling a wind power system comprising a plurality of system elements, the wind power system including a plurality of data processors distributed...
US-8,020,020 Fast, automatically scaled processor time stamp counter
In one embodiment, a processor comprises at least one processor time stamp counter (TSC) and a control unit coupled to the processor TSC. The processor TSC...
US-8,020,019 Managing voltage supply in multiple linked systems
In a data processing system having elements grouped into a plurality of power domains, each one of which has at least one processing element and at least two...
US-8,020,018 Circuit arrangement and method of operating a circuit arrangement
A circuit arrangement is provided comprising a first partial circuit to receive a supply voltage, a second partial circuit to receive an output signal of the...
US-8,020,017 Management of power domains in an integrated circuit
A method of operating a circuit, including operating in a first mode, wherein in the first mode, a first power domain operates in an active power mode and a...
US-8,020,016 Method for controlling electric power of computer system
To reduce the electric power consumption in a computer system having at least one server and at least one data processing apparatus, the data processing...
US-8,020,015 Method and apparatus for on-demand power management
An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution...
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