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| Patent # | Description |
|---|---|
| US-8,024,716 |
Method and apparatus for code optimization A system comprising a compiler that compiles source-level code to generate an intermediate-level instruction comprising a predetermined component. The... |
| US-8,024,715 |
Method and apparatus for detecting transient faults via dynamic binary
translation A method for detecting transient fault includes translating binary code to an intermediate language code. An instruction of interest in the intermediate... |
| US-8,024,714 |
Parallelizing sequential frameworks using transactions Various technologies and techniques are disclosed for transforming a sequential loop into a parallel loop for use with a transactional memory system. Open ended... |
| US-8,024,713 |
Using ghost agents in an environment supported by customer service
providers A method for supporting an application can include the step of receiving a problem indication relating to the application. The method can also identify a host... |
| US-8,024,712 |
Collecting application logs Techniques for locating and collecting application logs are disclosed. Embodiments disclosed herein can be advantageously utilized to collect application logs... |
| US-8,024,711 |
Software analysis tool A tool for analyzing software. The tool identifies calls to framework components made from within one or more application programs. The information may be... |
| US-8,024,710 |
Unwinding unwindable code Unwinding may take place in an annotated unwinding environment with non-annotated code by placing a context frame between a first annotated function and... |
| US-8,024,709 |
Facilitating assessment of a test suite of a software product Facilitating assessment of a test suite of a software product. In an embodiment, an inventory is maintained containing the features of the software product and... |
| US-8,024,708 |
Systems and methods for debugging an application running on a
parallel-processing computer system A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime... |
| US-8,024,707 |
Facilitating self-remediation for software applications Facilitating self-remediation for software applications. In an embodiment, a self-remediation tool (incorporated in the software application) receives a set of... |
| US-8,024,706 |
Techniques for embedding testing or debugging features within a service Techniques are presented for embedding testing and debugging features within a service. A user service is modified to include record and playback features. When... |
| US-8,024,705 |
System, method, and computer program product for distributed testing of
program code A system, method, and computer program product for distributed software code testing. When a data processing system is not being actively used, it will download... |
| US-8,024,704 |
Systems and methods for employing tagged types in a dynamic runtime
environment The present invention relates to systems and methods that facilitate dynamic programming language execution in a managed code environment. A class component is... |
| US-8,024,703 |
Building an open model driven architecture pattern based on exemplars View templates for use in generating application content are created by analyzing and categorizing existing application examples to derive reusable abstractions... |
| US-8,024,701 |
Visual creation of object/relational constructs Visual controls such as drag and drop are utilized to create object-oriented constructs from corresponding relational constructs, for instance. Similarly, an... |
| US-8,024,700 |
Method and system for understanding social organization in a design and
development process A method and system constructs a socio-technical network representing design and development processes. In one aspect, a network of inter-personal interactions... |
| US-8,024,699 |
Testing sub-systems of a system-on-a-chip using a configurable external
system-on-a-chip Mechanisms are provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The... |
| US-8,024,698 |
ASICs having more features than generally usable at one time and methods
of use More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted... |
| US-8,024,697 |
Various methods and apparatuses for estimating characteristics of an
electronic systems design Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system... |
| US-8,024,696 |
Clock speed for a digital circuit Various approaches for improving clock speed for a circuit design. In one embodiment, a graph having nodes and edges that represent the circuit design is... |
| US-8,024,695 |
Optimization of integrated circuit design and library A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of... |
| US-8,024,694 |
Systematic benchmarking system and method for standardized data creation,
analysis and comparison of... One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method... |
| US-8,024,693 |
Congestion optimization during synthesis One embodiment of the present invention provides a system that optimizes a circuit design during a logic design stage to reduce routing congestion during a... |
| US-8,024,692 |
Modeling the skin effect using efficient conduction mode techniques Described herein are embodiments of methods for extracting various high frequency parameters for a circuit design. In one exemplary embodiment, circuit design... |
| US-8,024,691 |
Automata unit, a tool for designing checker circuitry and a method of
manufacturing hardware circuitry... The present invention relates to an automata unit, a tool for designing circuitry and/or checker circuitry, and a method for manufacturing hardware circuitry.... |
| US-8,024,690 |
Method, system and computer program product for determining routing of
data paths in interconnect circuitry... A system, method and computer program product are provided for determining routing of data paths in interconnect circuitry for an integrated circuit. The method... |
| US-8,024,689 |
Semiconductor integrated circuit apparatus with low wiring resistance It is an object to provide a semiconductor integrated circuit which can easily be designed and has a low wiring resistance, and a method and apparatus for... |
| US-8,024,688 |
Deterring reverse engineering A method for detecting reverse engineering of a configuration bitstream for an integrated circuit is described. A user design is obtained. It is determined if... |
| US-8,024,687 |
Technology mapping for programmable logic devices using replicating logic
and parallel computations The present invention relates to a system for reducing the delay during technology mapping in FPGA that comprises locating and replicating the critical fan-in... |
| US-8,024,686 |
Retiming of multirate system Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a... |
| US-8,024,685 |
Delay analysis support apparatus, delay analysis support method and
computer product A delay analysis support apparatus that supports analysis of delay in a target circuit includes an acquiring unit that acquires error information concerning a... |
| US-8,024,684 |
Apparatus, method, and computer product for estimating power consumption
of LSI Design data of a cell group is copied to obtain design data of an antecedent cell group and of a subsequent cell group. Design data of a combinational circuit... |
| US-8,024,683 |
Replicating timing data in static timing analysis operation An apparatus, method and program product create multiple copies of a clock signal, or phase, to analyze timing operations within a single timing run of a static... |
| US-8,024,682 |
Global statistical optimization, characterization, and design For application to analog, mixed-signal, and custom digital circuits, a system and method to do: global statistical optimization (GSO), global statistical... |
| US-8,024,681 |
Hierarchical HDL processing method and non-transitory computer-readable
storage medium A Hardware Description Language (HDL) processing method is implemented in a computer and processes a HDL file which is written in HDL having a hierarchical... |
| US-8,024,680 |
Minimal leakage-power standard cell library A minimal leakage power Standard Cell Library is provided. The minimal leakage power Standard Cell Library provides minimal leakage power cells with improved... |
| US-8,024,679 |
Structure for apparatus for reduced loading of signal transmission
elements A design structure for a signal-handing apparatus or communication apparatus is provided which includes a common signal node operable to conduct a first signal,... |
| US-8,024,678 |
Interfacing with a dynamically configurable arithmetic unit An interface to a dynamically configurable arithmetic unit can include data alignment modules, where each data alignment module receives input variables being... |
| US-8,024,677 |
Methods and mechanisms for inserting metal fill data A method for implementing virtual metal fill includes obtaining a layout record for a circuit design, and inserting metal fill data into the layout record based... |
| US-8,024,676 |
Multi-pitch scatterometry targets The invention can provide a method of processing a substrate using multi-pitch scatterometry targets (M-PSTs) for de-convolving lithographic process parameters... |
| US-8,024,675 |
Method and system for wafer topography-aware integrated circuit design
analysis and optimization A method and system for designing an optimized specification of an integrated circuit (IC) is provided. The IC comprises a plurality of cells, and each of the... |
| US-8,024,674 |
Semiconductor circuit design method and semiconductor circuit
manufacturing method A computer converts dimensions of design patterns of components of the transistors configuring the semiconductor circuit or component parameters extracted from... |
| US-8,024,673 |
Layout evaluation apparatus and method An apparatus that evaluates a layout of a semiconductor integrated circuit by estimating a result of planarization in manufacturing the circuit includes a unit... |
| US-8,024,672 |
System and method for generating presentations A system and method allows a user to specify a presentation by arranging content into a hierarchical arrangement. The presentation is generated in response to... |
| US-8,024,671 |
Three-dimensional graphic user interface, and apparatus and method of
providing the same An apparatus and method for providing a three-dimensional graphic user interface includes a control module which creates a three-dimensional interface space... |
| US-8,024,670 |
Workflow management using live thumbnails A method for performing a task, which includes generating a user interface with multiple screens where each screen corresponds to a step in a workflow used for... |
| US-8,024,669 |
Image pickup apparatus An image pickup apparatus allows a user to quickly find a changed setting value in a list screen after the user changes the setting value of a desired setting... |
| US-8,024,668 |
Receiving and reporting page-specific user feedback concerning one or more
particular web pages of a website A method for receiving page-specific user feedback concerning a particular web page of a website includes using a comment icon viewable on the page to solicit... |
| US-8,024,667 |
In-document floating object re-ordering Techniques are disclosed herein for re-ordering floating objects in an electronic document. An electronic document having floating objects is displayed in a... |
| US-8,024,666 |
Apparatus and method for visualizing data A computer implemented method includes selecting a portion of a data set in a first visualization. A list of visualizations relevant to the context inferred... |
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