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Patent # Description
US-8,021,957 Process of forming an electronic device including insulating layers having different strains
An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies...
US-8,021,956 Ultrathin SOI CMOS devices employing differential STI liners
An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising...
US-8,021,955 Method characterizing materials for a trench isolation structure having low trench parasitic capacitance
Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower...
US-8,021,954 Integrated circuit system with hierarchical capacitor and method of manufacture thereof
A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal...
US-8,021,953 Method for making PMC type memory cells
A microelectronic device includes: at least one cell or element including at least one first electrode, at least one second electrode, and at least one stack of...
US-8,021,952 Integrated transistor, particularly for voltages and method for the production thereof
Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating...
US-8,021,951 Formation of longitudinal bipolar transistor with base region in trenches having emitter and collector regions...
Provided is a semiconductor device including: a silicon substrate; at least two trenches spaced apart from each other, being in parallel with each other, and...
US-8,021,950 Semiconductor wafer processing method that allows device regions to be selectively annealed following back end...
Disclosed are embodiments of a semiconductor wafer processing method that allow device regions to be selectively annealed following back end of the line (BEOL)...
US-8,021,949 Method and structure for forming finFETs with multiple doping regions on a same chip
A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and...
US-8,021,948 Scalable interpoly dielectric stacks with improved immunity to program saturation
A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on...
US-8,021,947 Method of forming an insulated gate field effect transistor device having a shield electrode structure
In one embodiment, a method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming...
US-8,021,946 Nonvolatile memory device and method for fabricating the same
A nonvolatile (e.g., flash) memory device includes a substrate having a plurality of isolation areas and active areas; a trench formed on the isolation area; a...
US-8,021,945 Bottle-shaped trench capacitor with enhanced capacitance
In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a...
US-8,021,944 Method for fabricating semiconductor device
A method for fabricating a semiconductor device is disclosed. The method includes: forming a photoresist film on a semiconductor substrate including a silicide...
US-8,021,943 Simultaneously formed isolation trench and through-box contact for silicon-on-insulator technology
A semiconductor fabrication method comprises providing a structure which includes a semiconductor substrate having a plurality of subsurface layers, the...
US-8,021,942 Method of forming CMOS device having gate insulation layers of different type and thickness
In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be...
US-8,021,941 Bias-controlled deep trench substrate noise isolation integrated circuit device structures
A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the...
US-8,021,940 Methods for fabricating PMOS metal gate structures
Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate...
US-8,021,939 High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods
A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the...
US-8,021,938 Semiconductor device and method for fabricating the same
A semiconductor device includes: a first gate insulating film on a first region of a semiconductor substrate; a first gate electrode on the first gate...
US-8,021,937 Array substrate including thin film transistor and method of fabricating the same
A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the...
US-8,021,936 Method of manufacturing thin film transistor
A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of...
US-8,021,935 Thin film device fabrication process using 3D template
A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template...
US-8,021,934 Method for making a transistor with metallic source and drain
A method including: making a structure on a substrate, said structure comprising at least a portion of a semiconductor material forming a channel of a field...
US-8,021,933 Integrated circuit including structures arranged at different densities and method of forming the same
A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which...
US-8,021,932 Semiconductor device, and manufacturing method therefor
To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the...
US-8,021,931 Direct via wire bonding and method of assembling the same
A method for electrically connecting an integrated circuit to a via in a substrate is disclosed. The method can include deforming a ball over the via to form a...
US-8,021,930 Semiconductor device and method of forming dam material around periphery of die to reduce warpage
A semiconductor device has a temporary carrier with a designated area for a first semiconductor die. A dam material is deposited on the carrier around the...
US-8,021,929 Apparatus and method configured to lower thermal stresses
An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The...
US-8,021,928 System and method for routing supply voltages or other signals between side-by-side die and a lead frame for...
An integrated circuit or chip includes a first die and a second die positioned on a lead frame of a package including a lead frame, such as a QFP, DIP, PLCC,...
US-8,021,927 Die down ball grid array packages and method for making same
A method of forming a ball grid array (BGA) package is provided. The method includes coupling an integrated circuit (IC) die to a heat spreader in an opening of...
US-8,021,926 Methods for forming semiconductor devices with low resistance back-side coupling
Electronic elements (40) with very low resistance back-side coupling are provided by forming one or more narrow trenches or pipes (411), preferably dielectric...
US-8,021,925 Thermal paste containment for semiconductor modules
A semiconductor module structure and a method of forming the semiconductor module structure are disclosed. The structure incorporates a die mounted on a...
US-8,021,924 Encapsulant cavity integrated circuit package system and method of fabrication thereof
A method for fabricating an encapsulant cavity integrated circuit package system includes: forming a first integrated circuit package with an inverted bottom...
US-8,021,923 Semiconductor package having through-hole vias on saw streets formed with partial saw
A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer having a plurality of die with contact pads disposed on a...
US-8,021,922 Remote chip attachment
A method of attaching a pair of chips, each having primary contacts that can be mated to each other, involves forming one or more secondary contacts on each of...
US-8,021,921 Method of joining chips utilizing copper pillar
A copper pillar may be provided on a chip and a first tin-containing layer may be provided over the copper pillar. A second tin-containing layer may be provided...
US-8,021,920 Method for producing a metal-ceramic substrate for electric circuits on modules
The invention relates to a metal-ceramic substrate for electric circuits or modules, the substrate including a ceramic layer which is provided with at least one...
US-8,021,919 Method of manufacturing a semiconductor device
A method of manufacturing a semiconductor device or a substrate is described. The method includes providing a chip attached to a carrier or providing a...
US-8,021,918 Integrated circuit chips with fine-line metal and over-passivation metal
An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon...
US-8,021,917 Semiconductor device and method for manufacturing the semiconductor device
An object is to suppress deterioration of element characteristics even when an oxide semiconductor is formed after a gate insulating layer, a source electrode...
US-8,021,916 Method for manufacturing semiconductor device
To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode...
US-8,021,915 Field effect transistor, method of producing the same, and method of producing laminated member
There is provided a field effect transistor having an organic semiconductor layer, including: an organic semiconductor layer containing at least porphyrin; and...
US-8,021,914 Manufacture of cadmium mercury telluride
A method of manufacture of cadmium mercury telluride (CMT) is disclosed. The method involves growing one or more buffer layers on a substrate by molecular beam...
US-8,021,913 Method and apparatus for forming the separating lines of a photovoltaic module with series-connected cells
For forming the separating lines, (5, 6, 7) which are produced in the functional layers (2, 3, 4) deposited on a transparent substrate (1) during manufacture of...
US-8,021,912 Method of fabricating an image sensor having an annealing layer
A method of manufacturing an image sensor is provided. In this method, a photoelectric conversion unit may be formed within a semiconductor substrate, wherein...
US-8,021,911 Method for producing a photovoltaic module
For producing a photovoltaic module (1), the front electrode layer (3), the semi-conductor layer (4) and the back electrode layer (5) are patterned by...
US-8,021,910 Method for producing single crystal silicon solar cell and single crystal silicon solar cell
A method for producing a single crystal silicon solar cell including the steps of: implanting ions into a single crystal silicon substrate through an ion...
US-8,021,909 Method for making a planar concentrating solar cell assembly with silicon quantum dots
Disclosed is a method for making a silicon quantum dot planar concentrating solar cell. At first, silicon nitride or silicon oxide mixed with silicon quantum...
US-8,021,908 Method and apparatus for dark current and blooming suppression in 4T CMOS imager pixel
A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a...
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