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Patent # Description
US-8,037,392 Method for optimizing the forward error correction scheme
The present invention relates to a method for optimizing the FEC scheme comprising the steps of (a) receiving a batch of data packets designated for...
US-8,037,391 Raid-6 computation system and method
One embodiment of the present invention sets forth a technique for performing RAID-6 computations using simple arithmetic functions and two-dimensional table...
US-8,037,390 Memory system and command handling method
A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error...
US-8,037,389 Method and apparatus to data encode and decode, storage medium having recorded thereon program to implement the...
A method of and apparatus to data encode and decode for improving the reliability of data that is compatible with a conventional error correction code (ECC)...
US-8,037,388 Method and device for layered decoding of a succession of blocks encoded with an LDPC code
The metrics matrix may include at least one particular layer including at least one particular column having several metrics cues, respectively, situated in...
US-8,037,387 Conversion device, conversion method, program, and recording medium
Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different...
US-8,037,386 TAP with select output from one of IR and DR
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
US-8,037,385 Scan chain circuit and method
A scan chain circuit is disclosed. The scan chain circuit includes a chain of serially coupled clocked circuits. In a first mode of operation, each of the...
US-8,037,384 Semiconductor device
A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit...
US-8,037,383 Gating circuitry coupling selected scan paths between I/O scan bus
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections....
US-8,037,382 Multi-mode programmable scan flop
A scannable flop circuit configured for operation in a multiple modes. The scannable flop circuit includes a functional flop having a data input, a clock input,...
US-8,037,381 Error detection, documentation, and correction in a flash memory device
A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data...
US-8,037,380 Verifying data integrity of a non-volatile memory system during data caching process
To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile...
US-8,037,379 Prediction of impact on post-repair yield resulting from manufacturing process modification
A method for predicting an impact on post-repair yield resulting from manufacturing process modification is described. The method includes receiving bit data...
US-8,037,378 Automatic test entry termination in a memory device
A memory device has a control register comprising a test mode disable bit. The test mode is initially enabled. If the device does not receive an appropriate key...
US-8,037,377 Techniques for performing built-in self-test of receiver channel having a serializer
A circuit includes a receiver channel and a built-in self-test circuit. The receiver channel has a serializer and a deserializer. The built-in self-test circuit...
US-8,037,376 On-chip failure analysis circuit and on-chip failure analysis method
An on-chip failure analysis circuit for analyzing a memory has a memory in which data is stored, a built-in self test unit which tests the memory, a failure...
US-8,037,375 Fast data eye retraining for a memory
A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The...
US-8,037,374 Communication terminal device and reception environment reporting method
A communication terminal device and a reception environment reporting method produce a more excellent throughput, by making a report of a reception environment...
US-8,037,373 Method of using link adaptation and power control for streaming services in wireless networks
A method for improving the performance for a streaming service by link-adaptation and power-control in a wireless packet network such as an Enhanced General...
US-8,037,372 Apparatus and method for testing setup/hold time
An apparatus for testing setup/hold time includes a plurality of data input units, each configured to calibrate setup/hold time of input data in response to...
US-8,037,371 Apparatus and method for testing high-speed serial transmitters and other devices
A testing device for testing a high-speed serial transmitter or other device includes an input stage having a first comparator, a second comparator, and a...
US-8,037,370 Data transmission apparatus with information skew and redundant control information and method
Apparatus and methods provide at least redundant control information such as control symbols and control data over respective channels, such as differential...
US-8,037,369 Error handling structure for use in a graphical program
System and method for error handling in a graphical program. An error handling structure is displayed in a graphical program. The error handling structure...
US-8,037,368 Controller capable of self-monitoring, redundant storage system having the same, and method thereof
A controller capable of self-monitoring, a redundant storage system having the same, and its method are proposed. Each controller is arranged with a...
US-8,037,367 Method and system for providing high availability to computer applications
A system and method for distributed fault detection. In an exemplary method, unplanned application exits and crashes may be detected at a node local level....
US-8,037,366 Issuing instructions in-order in an out-of-order processor using false dependencies
A mechanism is provided for issuing instructions. An instruction dispatch unit receives an instruction for dispatch to one of a plurality of execution units....
US-8,037,365 System and method for automated and adaptive threshold setting to separately control false positive and false...
Managing a computer system including automatically adjusting two separate component thresholds (a component threshold pair) based on a statistical model....
US-8,037,364 Forced management module failover by BMC impeachment consensus
A computer-implemented method, system and computer program product for managing failover of Management Modules (MMs) in a blade chassis are presented. Each...
US-8,037,363 Generation of trace elements within a data processing apparatus
A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises a device for performing a sequence of...
US-8,037,362 Storage system that finds occurrence of power source failure
One or more switches are interposed between a controller portion and a storage device. When transmission of a command to a certain storage device fails, a...
US-8,037,361 Selective write protect for disaster recovery testing
Various method, system, and computer program product embodiments for implementing selective write-protect by a processor in a data storage system within a...
US-8,037,360 Software testing framework for multiple operating system, hardware, and software configurations
Systems and methods are provided for testing software for use with a selected system configuration. The selected system configuration may include, for example,...
US-8,037,359 Operation management system having a process execution apparatus, information management apparatus, and process...
A process analyzing apparatus includes processing-identifying-information acquiring, from setting history information in which an update date and time,...
US-8,037,358 Semiconductor device and boot method for the same
A semiconductor device is designed to provide an access control for a memory that includes a plurality of storage regions storing the same boot programs...
US-8,037,357 System and method for generating test job control language files
A software testing system for generating a test job control language (JCL) file is provided. The system includes a processor, a memory device for storing a...
US-8,037,356 System and method for validating channel transmission
A system for validating communications between a plurality of processors is disclosed. The system includes a plurality of loop back paths, and each of the loop...
US-8,037,355 Powering up adapter and scan test logic TAP controllers
A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and...
US-8,037,354 Apparatus and method for operating a computing platform without a battery pack
An application control engine computing platform having a shut-down mechanism that permits the platform to adequately start up and operate upon return of power...
US-8,037,353 Method for operating a system
A method for operating a system, as well as a computer program and a computer program product for executing the method. In the method for operating a system,...
US-8,037,352 Method for auto power restoration
The present invention relates to an auto-restore method for a powered device by using a computer device to build a detecting/responding packet in an Ethernet...
US-8,037,351 Apparatus and methods for restoring system operation states
A process for restoring an operational state of a portable handheld device is provided. The device may include multiple computing units and persistent storage....
US-8,037,350 Altering a degree of redundancy used during execution of an application
Processor operating methods and integrated circuits are described. According to one embodiment, a processor operating method includes executing an application...
US-8,037,349 Data replication based on capacity optimization
A system and associated method for replicating data based on capacity optimization. A local node receives the data associated with a key. The local node within...
US-8,037,348 Vibration-aware data reassignment
An aspect of the present disclosure relates to implementing a temporary reassignment of data based on a vibration condition. An exemplary method includes...
US-8,037,347 Method and system for backing up and restoring online system information
A method and system for copying operating system information to said at least two storage devices, selectively hiding at least one, but not all, of the storage...
US-8,037,346 Avoiding a part of tape where error occurs by computing a number of records and a number of boundary marks...
A system for processing a data read error from a tape medium in one embodiment includes a reading section for reading data in data units from a tape medium; a...
US-8,037,345 Deterministic recovery of a file system built on a thinly provisioned logical volume having redundant metadata
A file server architecture decouples logical storage from physical storage and provides proactive detection and containment of faults, errors, and corruptions...
US-8,037,344 Method and apparatus for managing virtual ports on storage systems
A storage system is configured to create and manage virtual ports on physical ports. The storage system can transfer associations between virtual ports and...
US-8,037,343 Trap-based configuration audit
A method includes generating a layer three trap packet that includes an indicator that indicates an audit request of a resident configuration file, transmitting...
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