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| Patent # | Description |
|---|---|
| US-8,035,235 |
Integrated circuit packaging system with package-on-package and method of
manufacture thereof A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached... |
| US-8,035,234 |
Wiring substrate, manufacturing method thereof, and semiconductor device There is provided a wiring substrate for connecting a mounting board on one surface thereof and mounting an integrated circuit chip on the opposite surface to... |
| US-8,035,233 |
Adjacent substantially flexible substrates having integrated circuits that
are bonded together by non-polymeric... A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that... |
| US-8,035,232 |
Semiconductor device including interconnects, vias connecting the
interconnects and greater thickness of the... An interlayer insulating film is formed on the upper surface of a semiconductor substrate, and lower-level interconnects are formed in the interlayer insulating... |
| US-8,035,231 |
Semiconductor device and method of manufacturing the same The semiconductor device 1 includes interconnect layers 10, 20, an IC chip 30, via plugs 42, 44, a seal resin 50, and solder balls 60. The interconnect layer 10... |
| US-8,035,230 |
Semiconductor device and method for manufacturing same This invention discloses a semiconductor device including an insulating film having a recess therein; an electric conductor formed inside the recess; a... |
| US-8,035,229 |
Semiconductor device A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the... |
| US-8,035,228 |
High-density 3-dimensional resistors Interconnect, i.e., BEOL structures comprising at least one thin film resistor that is located at the same level as that of a neighboring conductive... |
| US-8,035,227 |
Top layers of metal for high performance IC's The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor... |
| US-8,035,226 |
Wafer level package integrated circuit incorporating solder balls
containing an organic plastic-core An integrated circuit including solder balls containing an elastic or resilient material core, a hard or rigid shell substantially enclosing the core, and an... |
| US-8,035,225 |
Semiconductor chip assembly and fabrication method therefor A semiconductor chip dual-sided assembly which has a higher degree of reliability of connections between semiconductor chips and a circuit substrate is... |
| US-8,035,224 |
Semiconductor device A semiconductor package includes a semiconductor chip having an integrated circuit, a functional element electrically coupled with the integrated circuit, and... |
| US-8,035,223 |
Structure and process for electrical interconnect and thermal management A structure and method for thermal management of integrated circuits. The structure for thermal management of integrated circuits includes first and second... |
| US-8,035,222 |
Semiconductor device A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in... |
| US-8,035,221 |
Clip mount for integrated circuit leadframes A leadframe having a die thereon connects a high current conductive area on the die to a leadframe contact using a copper clip that include a structural portion... |
| US-8,035,220 |
Semiconductor packaging device Embodiments of the invention relate to a semiconductor module and to a method for manufacturing a semiconductor module. In an embodiment of the invention, a... |
| US-8,035,219 |
Packaging semiconductors at wafer level A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming,... |
| US-8,035,218 |
Microelectronic package and method of manufacturing same A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135).... |
| US-8,035,217 |
Semiconductor device and method for manufacturing same A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then... |
| US-8,035,216 |
Integrated circuit package and method of manufacturing same Decoupling capacitors are frequently used in computer systems in order to control noise. In general, decoupling capacitors are placed as close as possible to... |
| US-8,035,215 |
Semiconductor device and manufacturing method of the same The invention is directed to prevent corrosion of a semiconductor device. In the semiconductor device manufacturing method of the invention, a semiconductor... |
| US-8,035,214 |
Conductive connecting pin for package substance A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical... |
| US-8,035,213 |
Chip package structure and method of manufacturing the same A chip package structure and a method of manufacturing the same are provided. The chip package structure includes a package portion and a plurality of external... |
| US-8,035,212 |
Semiconductor chip mounting body, method of manufacturing semiconductor
chip mounting body and electronic device According to one embodiment, a semiconductor chip mounting body, with an enhanced shock-resistance at portions of the bonding member corresponding to the... |
| US-8,035,211 |
Integrated circuit package system with support structure under
wire-in-film adhesive An integrated circuit package in package system including: providing a substrate; mounting a wire bonded die with an active side over the substrate; connecting... |
| US-8,035,210 |
Integrated circuit package system with interposer A method of manufacture of an integrated circuit package system includes: providing a base substrate; coupling a base integrated circuit on the base substrate;... |
| US-8,035,209 |
Micromechanical device which has cavities having different internal
atmospheric pressures A micromechanical device having a substrate wafer has at least one first cavity and one second cavity, the cavities being hermetically separated from each... |
| US-8,035,208 |
Integrated circuit package Package for an integrated circuit (IC), includes a housing (3) of a first material having two major surfaces (4, 5). The major surfaces are substantially... |
| US-8,035,207 |
Stackable integrated circuit package system with recess A stackable integrated circuit package system is provided including forming an external interconnect having an interconnect non-recessed portion and an... |
| US-8,035,206 |
Self-aligning structures and method for integrated circuits A lead frame having a die thereon connects a high current conductive area on the die to a lead frame contact using a copper clip that includes a structure... |
| US-8,035,205 |
Molding compound flow controller A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered... |
| US-8,035,204 |
Large die package structures and fabrication method therefor A method for fabricating large die package structures is provided wherein at least portions of the leadtips of at least a plurality of leadfingers of a... |
| US-8,035,203 |
Radio frequency over-molded leadframe package An over-molded leadframe (e.g., a Quad Flat No-lead (QFN)) package capable of operating at frequencies in the range of about five gigahertz (GHz) to about 300... |
| US-8,035,202 |
Electronic device having a wiring substrate A semiconductor chip of the present invention has a wiring substrate and a chip part. The wiring substrate has an insulating resin layer having a first major... |
| US-8,035,201 |
Reliable interconnection Embodiments relate to a method for forming reliable interconnects by the use of a device layer that can serve as a barrier or an etch stop layer, among other... |
| US-8,035,200 |
Neutralization of trapped charge in a charge accumulation layer of a
semiconductor structure A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped... |
| US-8,035,199 |
Semiconductor device and method for manufacturing the same A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a... |
| US-8,035,198 |
Through wafer via and method of making same A through wafer via structure. The structure includes: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through... |
| US-8,035,197 |
Electronic device and method for fabricating the same An electronic device has an element formed in the chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, a wire formed... |
| US-8,035,196 |
Methods of counter-doping collector regions in bipolar transistors The present invention provides a method of forming a bipolar transistor. The method includes doping a silicon layer with a first type of dopant and performing a... |
| US-8,035,195 |
Semiconductor element A semiconductor element includes a semiconductor layer having a first doping density, a metallization, and a contact area located between the semiconductor... |
| US-8,035,194 |
Semiconductor device and semiconductor package including the same Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at... |
| US-8,035,193 |
Method of fabricating capacitor in semiconductor device A capacitor includes a bottom electrode, a dielectric layer and a top electrode over a substrate. A Ru.sub.XTi.sub.YO.sub.Z film is included in at least one of... |
| US-8,035,192 |
Semiconductor device and manufacturing method thereof A semiconductor device has a semiconductor chip and through electrodes formed passing through the semiconductor chip. A ground layer connected to the through... |
| US-8,035,191 |
Contact efuse structure A contact efuse structure includes a silicon layer and a contact contacting the silicon layer with one end. When a voltage is applied to the contact, a void is... |
| US-8,035,190 |
Semiconductor devices A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector... |
| US-8,035,189 |
Semiconductor constructions The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can... |
| US-8,035,188 |
Semiconductor device Plural I/O cells (14) having electrode pads for wire bonding (13) are disposed with spaces (55) between them in the vicinity of a corner of an I/O region (11)... |
| US-8,035,187 |
Semiconductor light receiving element and optical communication system The present invention provides a semiconductor light receiving element capable of reducing capacity while minimizing increase in travel time of carriers. The... |
| US-8,035,186 |
Low-noise semiconductor photodetectors A photodetector is formed from a body of semiconductor material substantially surrounded by dielectric surfaces. A passivation process is applied to at least... |
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