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Patent # Description
US-8,051,343 Method of testing a memory module and hub of the memory module
Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input...
US-8,051,342 Semiconductor memory device
A semiconductor memory device including: a memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells arranged in...
US-8,051,341 Semiconductor memory device having test address generating circuit and method of testing semiconductor memory...
A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of...
US-8,051,340 System and method for balancing delay of signal communication paths through well voltage adjustment
A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to...
US-8,051,339 Data preserving method and data accessing method for non-volatile memory
A data preserving method and a data accessing method for a non-volatile memory are provided. In the data preserving method, a data is checked according to an...
US-8,051,338 Inter-asic data transport using link control block manager
An apparatus includes a SerDes circuit and a link control block (LCB). The SerDes circuit is a first end of a SerDes circuit pair of a SerDes lane. A SerDes...
US-8,051,337 System and method for fast cache-hit detection
A system and method for fast detection of cache memory hits in memory systems with error correction/detection capability is provided. A circuit for determining...
US-8,051,336 Recording method for video/audio data
In order to provide a recording method for data which have been or are being generated at a data source in a time sequenced manner and are transmitted via a...
US-8,051,335 Recovery from transitory storage area network component failures
Lun communications between a storage server and a storage subsystem for a particular lun are assigned both a current path and an alternate path. Lun...
US-8,051,334 Enabling SAS expander loops for increased fairness and performance
The use of loops in SAS networks is enabled by designating ports connected to loop connections as table loop ports (TLPs). Under normal operating conditions,...
US-8,051,333 Memory failure recovery method, information processing apparatus, and program
Upon occurrence of a memory error which is difficult to correct, CPU interrupts a process under execution in response to interrupt signal output from error...
US-8,051,332 Exposing application performance counters for .NET applications through code instrumentation
Disclosed is a method for adding performance counters to a .NET application after compilation of the .NET application to Common Intermediate Language code...
US-8,051,331 Memory card and its initial setting method
In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check...
US-8,051,330 Fault location in telecommunications networks using bayesian networks
A method for locating a fault in a communication network, includes receiving status information relating to alarms, events, polled statuses or test results in...
US-8,051,329 Method and system for initializing a computing system
Method and system for executing instructions out of a non-volatile memory that may have defective blocks is provided. During an initialization process, a...
US-8,051,328 Recovering from a system failure
On or more techniques and/or systems are provided for rapidly resuming processing of client requests after a system failure event. Accordingly, during a boot-up...
US-8,051,327 Connection between machines and power source
Machines may be connected to power distribution units (PDU/STSs) in such a way that if one PDU/STS fails or is taken out of service, the machines' loads are...
US-8,051,326 System and method for completeness of TCP data in TCP HA
System and method for completeness of transmission control protocol (TCP) high availability (HA) are disclosed. The system includes an active processor, having...
US-8,051,325 Multiprocessor system and failure recovering system
A multiprocessor system includes a plurality of nodes, each of which includes a plurality of processors, a plurality of memories, and first and second node...
US-8,051,324 Master-slave provider architecture and failover mechanism
Described are techniques for executing an application on two or more processors. A first portion of one or more modules of the application is determined. A...
US-8,051,323 Auxiliary circuit structure in a split-lock dual processor system
A multiple-processor system 2 is provided where each processor 4-0, 4-1 can be dynamically switched between running in a locked mode where one processor 4-1...
US-8,051,322 Redundant failover system, redundancy managing apparatus and application processing apparatus
In a communication system using an IP tunnel for communication between application processing apparatuses (hereinafter, processing apparatuses), an application...
US-8,051,321 Cluster system and node switching method
When a first server node fails in a cluster system, a client node device transmits failure detection information to a second server node device. Upon receipt of...
US-8,051,320 Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof
The present invention provides a clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof. In an embodiment, a...
US-8,051,319 Method for power management for computer system
The invention provides a method for power management for a computer system. In one embodiment, the computer system comprises a system controller, a chipset, and...
US-8,051,318 Method and apparatus for controlling power in a battery-powered electronic device
A method for controlling power in a battery-powered electronic apparatus is disclosed. The electronic apparatus includes a battery, a detection unit and a power...
US-8,051,317 Power supply with remotely adjustable output
A power supply system allowing remote adjustments of the power output of the power supply unit without having to physically access the power supply unit itself...
US-8,051,316 System and method for managing power supply units
Systems and methods for power management in an information handling system are disclosed. A method may include determining a power requirement of resources...
US-8,051,315 Power throttling apparatus
Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow...
US-8,051,314 Serial ATA (SATA) power optimization through automatic deeper power state transition
A host device and a storage device with a Serial ATA (SATA) architecture to independently transition to a deeper low power state after first entering an initial...
US-8,051,313 Apparatus, system and method of power state control
An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for...
US-8,051,312 Apparatus and method for reducing power consumption by an integrated circuit
An integrated circuit includes an energy controller that generates a power supply voltage level for the integrated circuit based on a desired target frequency...
US-8,051,311 Power supply circuit for central processing unit
A power supply circuit for a CPU includes a first control circuit, a switch circuit, an operational amplifying circuit, and a second control circuit. The first...
US-8,051,310 Method for reducing power consumption of processor
A method for reducing power consumption of a processor is disclosed comprising steps of applying time-frequency transformation to a plurality of load values of...
US-8,051,309 Method and apparatus to combine power and control signals in a mobile computing device
A mobile computing device is described that includes multiple device components, a power supply and a power line connected to each device component. The power...
US-8,051,308 Display device with USB connectivity
A method to power an electronic device through an electrical connection port of a display device, includes electrically connecting a display device to a first...
US-8,051,307 Voltage-controlled device, method and computer device capable of dynamically regulating voltage and effectively...
The invention provides a voltage-controlled device, method and computer device capable of dynamically regulating voltage and effectively saving energy. The...
US-8,051,306 Portable computer with shared hardware resources
The invention provides a portable computer with shared hardware resources that can be used by other computers. The portable computer includes an interface...
US-8,051,305 Motherboard device and computing apparatus capable of selectively controlling electric power supplied to one of...
A motherboard device includes a first connecting interface coupled to a first graphics card, a second connecting interface coupled to a second graphics card, a...
US-8,051,304 Power supply apparatus with system controller
In a power supply apparatus for supplying a target power supply voltage to a microprocessor, a system controller sets the target power supply voltage to be...
US-8,051,303 Secure read and write access to configuration registers in computer devices
The disclosed embodiments relate to a secure configuration space for a computing device. Each of the configuration resisters in a configuration space are...
US-8,051,302 Data distributing system and recording medium used for it
Encrypted music data and additional information necessary for accessing a server (30) are copied from a CD-ROM (200) onto a memory card (110). The memory card...
US-8,051,301 Memory management system and method providing linear address based memory access security
A memory management unit (MMU) is disclosed for managing a memory storing data arranged within a plurality of memory pages. The MMU includes a security check...
US-8,051,300 System and method for reducing latency on remotely-booted information handling systems
Systems and methods for reducing latency on a remotely-booted information handling system are disclosed. A method may include remotely booting an information...
US-8,051,299 Computer security method and computer system
A method for secure loading, integrity checking of the runtime image and control over the runtime execution of applications which ensures that a software...
US-8,051,298 Integrated fingerprinting in configuration audit and management
A system and computer implemented method for identifying active applications in an enterprise computing system is provided. The method includes defining a...
US-8,051,297 Method for binding a security element to a mobile device
According to an aspect of the present invention there is provided a method of binding a security element to a device, comprising: generating a passkey to...
US-8,051,296 System and method for initializing secure communications with lightweight devices
System and methods for initializing secure communications with lightweight devices are described herein. In one embodiment, the method includes enabling a...
US-8,051,295 Benchmarks for digital watermarking
The presently claimed invention relates generally to digital watermarking of data, e.g., representing video or audio. One claim recites a method including:...
US-8,051,294 Methods for audio watermarking and decoding
The presently claimed invention relates generally to encoding and decoding audio signals to include auxiliary information. One example encoding technique...
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