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Patent # Description
US-8,069,393 Method and system for providing long and short block length low density parity check (LDPC) codes
An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem...
US-8,069,392 Error correction code system and method
An error correction code system includes an error correction code generator for generating an error correction code based on a data unit and an error detector...
US-8,069,391 Error correction using error detection codes
A method, apparatus, and computer-readable media comprises receiving a detected sequence representing a signal on a channel, wherein the detected sequence...
US-8,069,390 Universal error control coding scheme for digital communication and data storage systems
The universal forward error-correction coding system provides adjustable code rates and coding gains to greatly benefit the design of many modern digital...
US-8,069,389 Error correction circuit and method, and semiconductor memory device including the circuit
An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error...
US-8,069,388 Distributed block coding (DBC)
Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source...
US-8,069,387 Turbo coding having combined turbo de-padding and rate matching de-padding
Turbo coding having combined turbo de-padding and rate matching de-padding. An approach is presented by which a singular module is operable to perform both zero...
US-8,069,386 Semiconductor device
A semiconductor device includes a CPU, a memory, a memory BIST circuit, a first selector that selects and outputs an address and control signal from the memory...
US-8,069,385 Programmable built-in self-test architecture
A PBIST architecture is described. A data path circuit is configured for bit-to-associated bit comparisons of expected result data read from a tile with the...
US-8,069,384 Scanning reassigned data storage locations
An aspect of the present disclosure relates to scanning reassigned data storage locations. In one example, a reassignment table is accessed to identify a...
US-8,069,383 Apparatus, system, and method for bad block remapping
An apparatus, system, and method are disclosed for bad block remapping. A bad block identifier module identifies one or more data blocks on a solid-state...
US-8,069,382 Memory cell programming
Embodiments of the present disclosure provide methods, devices, and systems for performing a programming operation on an array of non-volatile memory cells. One...
US-8,069,380 Method, system and computer-readable code to test flash memory
A flash memory device includes a flash memory residing on at least one flash memory die. The flash memory device also includes a flash controller residing on a...
US-8,069,379 Memory system with point-to-point request interconnect
A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over...
US-8,069,378 Method and apparatus for evaluating and optimizing a signaling system
A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the...
US-8,069,377 Integrated circuit having memory array including ECC and column redundancy and method of operating the same
An integrated circuit device (for example, a logic device or a memory device (such as, a discrete memory device)), including a memory cell array having a...
US-8,069,376 On-line testing for decode logic
Methods and apparatuses for on-line testing for decode logic are presented. In one embodiment, a processor comprises translation logic to decode an instruction...
US-8,069,375 Cover lover
The present invention relates to a method, device, and system for managing verification of configurable hardware and software. The solution according to the...
US-8,069,374 Fingerprinting event logs for system management troubleshooting
A technique for automatically detecting and correcting configuration errors in a computing system. In a learning process, recurring event sequences, including...
US-8,069,373 Method for debugging reconfigurable architectures
A method for debugging reconfigurable hardware is described. According to this method, all necessary debug information is written in each configuration cycle...
US-8,069,372 Simulated computer system for monitoring of software performance
A system S is defined which is capable of simulating a computer (virtual computer, VC) for the purpose of software performance monitoring. The system is...
US-8,069,371 Method and system for remotely debugging a hung or crashed computing system
A method and system for debugging a computer upon a kernel hang and/or upon a software failure, the method comprising executing a debugger on a remote computer,...
US-8,069,370 Fault identification of multi-host complex systems with timesliding window analysis in a time series
A method and apparatus is provided for determining the most probable cause of a problem observed in a complex multi-host system. The approach relies on a...
US-8,069,369 Remote anomaly diagnosis and reconfiguration of an automatic data collection device platform over a...
The invention provides a system and method for remotely diagnosing and repairing a plurality of device platforms. A remote service technician utilizes a...
US-8,069,368 Failover method through disk takeover and computer system having failover function
When a primary server executing a task fails in a computer system where a plurality of servers are connected to an external disk device via a network and the...
US-8,069,367 Virtual lock stepping in a vital processing environment for safety assurance
An apparatus and method for train control utilizing virtual lock stepping are disclosed. In accordance with the illustrative embodiment, an improved method of...
US-8,069,366 Global write-log device for managing write logs of nodes of a cluster storage system
A cluster system comprises a plurality of nodes that provides data-access service to a shared storage, each node having at least one failover partner node for...
US-8,069,365 Method and device for realizing IP multimedia subsystem disaster tolerance
A method for realizing an Internet protocol (IP) multimedia subsystem (IMS) disaster tolerance includes the steps as follows. An S-CSCF receives a user...
US-8,069,364 Method to recover from logical path failures
A system and method for recovering from logical path failures is set forth. More specifically, when a host detects a logical path failure, the host enters a...
US-8,069,363 Double data rate output latch for static RAM device has edge-triggered flip-flop to output DDR signal to...
A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized...
US-8,069,362 Automated electrical power savings in virtualization environments
Methods and apparatus, including computer program products, are provided for shutting down a host, such as a computer, server, and the like, to enable power...
US-8,069,361 Method and program for setting microprocessor power supply voltage
A determining unit determines the state of the microprocessor. A setting unit sets a power supply voltage to be supplied to the microprocessor according to the...
US-8,069,360 Apparatus, method and computer program for processing information
An information processing apparatus working in pause states containing at least both a suspension state and a hibernation state, may include a time counting...
US-8,069,359 System and method to establish and dynamically control energy consumption in large-scale datacenters or IT...
A system and method for establishing and dynamically controlling energy consumption in large-scale datacenters or IT infrastructures. The system including a...
US-8,069,358 Independent power control of processing cores
Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least...
US-8,069,357 Multi-processor control device and method
A multi-processor control device according to an example of the invention comprises a cooperative control unit which determines priorities of requests issued...
US-8,069,356 Accessory power management
Methods, apparatus, and circuits for managing power among portable computing devices and one or more accessories. One example provides commands to improve power...
US-8,069,355 Data path controller with integrated power management to manage power consumption of a computing device and its...
A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to...
US-8,069,354 Power management for system having one or more integrated circuits
Power management control software including power management policies is provided with those policies divided into observation code and response code. When...
US-8,069,353 Low-latency data decryption interface
Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of...
US-8,069,352 Device, system and method for timestamp analysis of segments in a transmission control protocol (TCP) session
A method performed in an intrusion detection/prevention system, a system or a device for determining whether a transmission control protocol (TCP) segment in a...
US-8,069,351 Remote control device
Methods, systems, devices, and memory are disclosed for remote controlling consumer electronics devices. Different orientations of a remote control device are...
US-8,069,350 Communication protocol and electronic communication system, in particular authentication control system, as...
In order to provide a communication protocol for cryptographic authentication on the basis of at least one cryptographic algorithm, in particular according to...
US-8,069,349 Method of secure file transfer
A method of securely transferring files from an un-trusted to a trusted network is disclosed. A file that is an archive file of many component files is...
US-8,069,348 Client digital program insertion in a conditional access module
Systems and methods are disclosed for inserting programs into broadcasted primary programs by a conditional access (CA) module that is inserted into a host...
US-8,069,347 Method for the application of implicit signature schemes
A method of verifying a transaction over a data communication system between a first and second correspondent through the use of a certifying authority. The...
US-8,069,346 Implicit certificate verification
A method of computing a cryptographic key to be shared between a pair of correspondents communicating with one another through a cryptographic system is...
US-8,069,345 Methods and systems for recovering a computer system using boot volume data from a storage area network
Methods and systems for recovering and booting a computer system using a SAN. The computer system comprises a local storage device. A request for writing data...
US-8,069,344 System and method for analyzing CPU performance from a serial link front side bus
Monitoring of boot progress for a multiprocessor information handling system is performed with a test module running on a CPLD. RAM integrated in the CPLD...
US-8,069,343 Computer with bootable restoration
A bootable restoration computer includes: at least one mass storage device; at least two mass storage device partitions in the at least one mass storage device,...
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