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Circuit providing load isolation and memory domain translation for memory
A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of...
Systems, methods and devices for arbitrating die stack position in a
multi-die stack device
Embodiments are described for arbitrating stacked dies in multi-die semiconductor packages. In one embodiment, die identification data for at least two stacked...
Row address decoder and semiconductor memory device having the same
A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals....
Line driver circuit and method with standby mode of operation
A line driver circuit can include an integrated circuit substrate of a first conductivity type having at least a first and a second well of a second...
Semiconductor memory device
A semiconductor memory device includes a first write bit line, a second write bit line, a write word line, a first read bit line, a read word line, and a memory...
Electronic equipment system and semiconductor integrated circuit
An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the...
Fuse element reading circuit
A fuse element reading circuit including a first fuse element having a resistance which differs in accordance with whether the first fuse element is in a blown...
Logic embedded memory having registers commonly used by macros
A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The...
Dynamic semiconductor memory with improved refresh mechanism
Various embodiments for implementing refresh mechanisms in dynamic semiconductor memories that allow simultaneous read/write and refresh operations. In one...
Sense amplifier circuit and semiconductor memory device
A single-ended sense amplifier circuit comprises first and second MOS transistors and first and second voltage setting circuits. The first MOS transistor...
Semiconductor storage device having redundancy area
A semiconductor storage device is provided with: a memory cell array which includes a normal area and a redundancy area which replaces a defective memory cell...
Memory control circuit and memory control method
A memory control circuit includes a data sample circuit, a first delay control circuit, a second delay control circuit and a data circuit. The data sample...
Operation guarantee system
An operation guarantee system includes a decoder circuit, a comparison circuit, a CPU circuit, a frequency adjustment circuit and a DQ adjustment circuit. The...
Semiconductor memory device
A semiconductor memory device includes a memory cell provided at an intersection of a word line and a bit line, a precharge circuit connected to the bit line, a...
Data alignment circuit and method of semiconductor memory apparatus
A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe...
Semiconductor memory device that can perform successive accesses
To provide an input/output circuit that includes a write path to which write data is supplied and a read path to which read data is supplied and first and...
System and method for reducing pin-count of memory devices, and memory
device testers for same
Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output...
Memory device with parallel interface
A memory device including a serial-parallel conversion section that converts serial data into parallel data, a parallel-serial conversion section that converts...
Dual-threshold-voltage two-port sub-threshold SRAM cell apparatus
The invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second...
Tracking cells for a memory system
Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used...
Memory block reallocation in a flash memory device
A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability....
Array of non-volatile memory cells including embedded local and global
reference cells and system
An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth...
NAND with back biased operation
Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are...
Method and apparatus for programming nonvolatile memory
A nonvolatile memory has logic which performs a programming operation, that controls a series of programming bias arrangements to program at least a selected...
Sensing of memory cells in NAND flash
An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells...
NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory
array, and a method of forming a NAND...
A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast,...
Program and erase methods with substrate transient hot carrier injections
in a non-volatile memory
The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron...
Nonvolatile semiconductor memory
Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and...
Nonvolatile semiconductor memory device
A memory cell array including at least one memory cell, an address storage section containing address information, an address judging circuit for judging...
FLOTOX type EEPROM
A FLOTOX EEPROM of the invention includes: a plurality of floating gates 11 arranged in array, each having a tunnel window 12 and allowing electron injection...
Semiconductor memory device and method for driving semiconductor memory
A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control...
Method and system of finding a read voltage for a flash memory
A method and system of finding a read voltage for a flash memory is disclosed. Data are read from array cells of the flash memory with a default read voltage,...
Multi-bit flash memory devices and methods of programming and erasing the
A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit...
Memory device and methods for fabricating and operating the same
The memory device is described, which includes a substrate, a conductive layer, a charge storage layer, a plurality of first doped regions and a plurality of...
Memory employing redundant cell array of multi-bit cells
A memory that employs a redundant cell array for recovery of one or more failed core cell arrays of multi-bit memory cells is described. The memory includes a...
Method for creating nonequilibrium photodetectors with single carrier
A method of forming a diode comprises the steps of forming an extraction region of a first conductivity type, forming an active region of a second conductivity...
Magnetic element having perpendicular anisotropy with enhanced efficiency
Techniques and magnetic devices associated with a magnetic element that includes a fixed layer having a fixed layer magnetization and perpendicular anisotropy,...
Semiconductor integrated circuit device
The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin...
Semiconductor memory device
The semiconductor memory device includes: an inverter pair of a cross-coupled first and second inverters; a first transfer transistor including a front gate and...
SRAM cell without dedicated access transistors
A Static Random Access Memory (SRAM) cell without dedicated access transistors is described. The SRAM cell comprises a plurality of transistors configured to...
Memory with five-transistor bit cells and associated control circuit
Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a...
Biploar resistive-switching memory with a single diode per memory cell
According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element...
Semiconductor memory device having DRAM-compatible addressing mode and
data processing system including same
In synchronism with an active command, a row address and a column address are simultaneously received, and a page address is received in synchronism with a read...
High density resistance based semiconductor device
Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells located between word...
Integrated circuit with resistive memory cells and method for
An integrated circuit including a resistive memory cell and a method of manufacturing the integrated circuit are described. The integrated circuit comprises a...
Method of making nonvolatile memory device containing carbon or nitrogen
A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a silicon, germanium...
High speed FRAM including a deselect circuit
High speed FRAM including a deselect circuit is realized for replacing SRAM, wherein the deselect circuit is connected to a local bit line pair for forcing a...
Resistance-change memory device
A resistance-change memory device is provided and includes a stack constituting a tunnel magnetoresistance effect element that has a magnetic layer in which a...
Flash memory module
An embedded processor system including a flash process semiconductor die and a digital process semiconductor die. The flash process semiconductor die includes...
Synchronous rectifying for soft switching power converters
An synchronous rectifying apparatus or synchronous rectifying circuit of a soft switching power converter is provided to improve the efficiency. The integrated...