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Decoding device and receiving device
A decoding apparatus for low density parity check codes includes a variable-to-check message generator and a check-to-variable message generator. The...
Method and device for transmitting data according to a hybrid ARQ method
To achieve a greater flexibility when transmitting data according to a hybrid ARQ method, preferably when used in a mobile radio system, a channel-coded bit...
User equipment using hybrid automatic repeat request
A user equipment comprises a transmitter and an adaptive modulation and coding controller. The transmitter is configured to transmit data over an air interface...
Communication method and communication device
A request change unit outputs a command as a request under control of a judgment control unit. A response condition determination unit determines a condition...
Decoding apparatus and method thereof
In a decoding apparatus in a portable Internet terminal, a channel encoded symbol received from a transmitter is decoded by one of a chase-combining scheme and...
Method and system for supporting multiple hybrid automatic repeat request
processes per transmission time interval
A method and system for supporting multiple hybrid automatic repeat request (H-ARQ) processes per transmission time interval (TTI) are disclosed. A transmitter...
Error correction apparatus and method for digital device
An improved error correction apparatus and method for a digital device are provided. An error correction apparatus includes at least one client module...
Apparatus and method for testing and debugging an integrated circuit
An integrated circuit includes an embedded processor. An embedded in-circuit emulator is located within the embedded processor. The embedded in-circuit emulator...
Pattern generator and memory testing device using the same
An address operation circuit generates a row address which indicates an address in memory under test to be accessed. The row address memory stores the row...
Method and apparatus for testing delay faults
An apparatus or method for testing of a SOC processor device may minimize interference that is caused by interfacing a comparatively low-speed testing device...
Protecting data on integrated circuit
Various example embodiments are disclosed. According to one example embodiment, an integrated circuit may include a mode block, a plurality of data blocks, and...
Generic debug external connection (GDXC) for high integration integrated
A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface...
A test apparatus includes a test section that executes testing of each cell of the memory under test, a fail information storage section that stores fail...
Memory apparatus and method and reduced pin count apparatus and method
A memory apparatus is disclosed, comprising a memory device under test, a reduced-pin-count device and a built-in self test device. The reduced-pin-count device...
Block management and replacement method, flash memory storage system and
controller using the same
A block management and replacement method for a flash memory is provided. The method includes grouping physical blocks of the flash memory into physical units...
Signal analyzing apparatus
The present invention is to provide a signal analyzing apparatus which can easily identify a pattern high in error rate and a pattern causing bit errors in...
Non-intrusive eye monitor system
A signal receiver includes a data recovery module that generates an equalized data signal and a recovered data signal based on a data input signal. An error...
Apparatus and method for transmitting and receiving data bits
Provided are an apparatus and method for transmitting and receiving data bits. The apparatus includes a transmitter configured to generate a transmission signal...
Visualization of user interactions in a system of networked devices
As set forth herein, a system identifies soft failures of devices. An interface captures transactional data between one or more users and one or more devices...
Multi-CPU failure detection/recovery system and method for the same
A multi-CPU system including plural CPUs, comprising a failure state detection unit for detecting a failure in an operating program, and a recovery unit for...
Program failure recovery
A program failure is detected during programming of a memory device. When the program failure is detected, a transfer of the contents of a register of the...
Automated information technology error and service request correlation
An implementation verification policy for each of a set of change management tasks associated with one of a set of service requests within an information...
Method for recognizing a power failure in a data memory and recovering the
To detect a power failure in a volatile data memory containing useful data units and test data units associated with the useful data units, the associated test...
Method and apparatus for providing a multi-scope bug tracking process
A process capable of tracking bugs across multiple product releases using multiple scopes is disclosed. Upon receipt of a bug report, a process creates a defect...
Method for influencing a control unit and manipulation unit
A method for influencing a control unit by means of a manipulation unit whereby the control unit has at least one microcontroller, at least one memory having a...
Inference of contract using declarative program definition
A declarative program definition. The definition is analyzed to produce an application contract that describes semantics for sending and receiving application...
Exception raised notification
An exception notification system is described herein that provides an early notification that a software exception has occurred before exception handling code...
Methods, media and systems for detecting anomalous program executions
Methods, media, and systems for detecting anomalous program executions are provided. In some embodiments, methods for detecting anomalous program executions are...
Motherboard error detection system
A motherboard error detection system includes a pluggable error detection board and a motherboard having a boot management chip. When the motherboard enters a...
System and method for data protection against power failure during sector
Disclosed herein is a technique to protect sector remapped boundary data from corruption due to catastrophic errors such as loss of power in storage disks...
Memory backup used in a raid system
Systems, apparatuses, and methods for memory backup in a redundant array of independent disks (RAID) system are described. The methods include detecting a...
System and method for responding to failure of a hardware locus at a
A method for responding to a failure of hardware locus of at a communication installation having a plurality of control apparatuses for controlling a plurality...
Enhancing reliability of a many-core processor
In one embodiment, the present invention includes a method for identifying available cores of a many-core processor, allocating a first subset of the cores to...
Third-party voting to select a master processor within a multi-processor
Techniques are described of using votes of third-party components to select a master processor from a plurality of redundant processors. A master processor and...
Storage controller and storage control method
Spare disk drives are provided to a chassis for storing storage devices, and, when any one of the storage devices configuring RAID fails, the storage controller...
Failover and recovery for replicated data instances
Replicated instances in a database environment provide for automatic failover and recovery. A monitoring component can periodically communicate with a primary...
Storage control device and RAID group extension method
The present invention provides a storage system having a controller that can extend an old RAID group to a new RAID group without decreasing a processing speed....
High data availability SAS-based RAID system
A storage system includes two RAID controllers, each having two SAS initiators coupled to a zoning SAS expander. The expanders are linked by an inter-controller...
Controlling apparatus and controlling method
A controlling apparatus for controlling a disk array unit includes a cache memory for caching data of the disk array unit; a nonvolatile memory for storing the...
Data corruption diagnostic engine
A computer is programmed to execute a diagnostic procedure either on a pre-set schedule or asynchronously in response to an event, such as an error message, or...
Method for reactivating at least one media transfer protocol-compatible
device when an unrecoverable error...
A method for reactivating at least one media transfer protocol-compatible (MTP-compatible) device when an unrecoverable error occurs includes: temporarily...
Systems and methods for handling path failures to active-passive storage
A computer-implemented method for handling path failures to active-passive storage arrays may include identifying a host system with multiple I/O paths to an...
Method and apparatus for restore management
A restore management apparatus comprising a restore performing unit which performs restoration of a data and stores the data in a restore disk which is distinct...
Failure recovery method, failure recovery program and management server
In a computer system including server apparatuses such as an active server and a standby server connected to a storage apparatus, when the active server fails,...
Control method for information processing system, information processing
system, and program
An object of the present invention is to ensure, in an information processing system including a plurality of server apparatuses coupled to one another,...
Meta-instrumentation for security analysis
A system and method for analyzing and/or testing member devices in a multi-device system. The multi-device system includes a device-under-analysis (DUA) and a...
Semiconductor integrated circuit, memory system, memory controller and
memory control method
Aspects of the embodiment provide a semiconductor integrated circuit including a control terminal coupled to a memory through a control bus, a data terminal...
Method for ensuring synchronous presentation of additional data with audio
A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing...
Session redundancy using a replay model
A mechanism for synchronizing states of components in a first routing engine to corresponding components in a second routing engine is provided. In order to...
Method and system for optimizing the completion of computing operations
Computer software that manages the amount of power provided to a processing unit for a specific process task, optimizing the processing speed of that specific...