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Patent # Description
US-8,077,538 Address decoder and/or access line driver and method for memory devices
Address decoders and access line drivers are provided. One such row decoder and access line driver receives power supply voltages in a manner that prevents CHC...
US-8,077,537 Memory device, memory controller and memory system
Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory...
US-8,077,536 Method of operating semiconductor memory device with floating body transistor using silicon controlled...
A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being...
US-8,077,535 Memory refresh apparatus and method
A system and method are provided. The system and method simulate a DRAM memory circuit using an interface circuit connected to a plurality of other DRAM memory...
US-8,077,534 Adaptive noise suppression using a noise look-up table
A proactive noise suppression system and method for a power supply network of an integrated circuit. The system and method include receiving an IC event...
US-8,077,533 Memory and method for sensing data in a memory using complementary sensing scheme
In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic...
US-8,077,532 Small unit internal verify read in a memory device
Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of...
US-8,077,531 Semiconductor integrated circuit including column redundancy fuse block
A semiconductor integrated circuit includes a semiconductor chip having an edge area and a bank area located an inner portion of the edge area, and a column...
US-8,077,530 Semiconductor memory device
A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for...
US-8,077,529 Circuit and method for outputting data in semiconductor memory apparatus
A data output circuit of a semiconductor memory apparatus includes a pre-driver generating pull-up and down signals from driving rising and falling data in...
US-8,077,528 Low couple effect bit-line voltage generator
A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a...
US-8,077,527 SRAM leakage reduction circuit
A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A...
US-8,077,526 Low power SSTL memory controller
An integrated circuit device having configurable resources is configured as a memory controller that includes a plurality of bi-directional pins, an input...
US-8,077,525 Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes: a memory cell array configured to have a plurality of blocks arranged thereon, each of the blocks being...
US-8,077,524 Correcting for over programming non-volatile storage
A non-volatile storage system corrects over programed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage...
US-8,077,523 Semiconductor memory device with a stacked gate including a charge storage layer and a control gate and method...
A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to...
US-8,077,522 Memory and method operating the memory
A memory comprises a memory array, a sense unit, and a biasing and shielding circuit. The biasing and shielding circuit is coupled to the memory array and the...
US-8,077,521 Bitline current generator for a non-volatile memory array and a non-volatile memory array
A bitline current generator, for a non-volatile memory array which comprises a plurality of memory bitcells and bitlines, comprises a switching means for each...
US-8,077,520 Determining threshold voltage distribution in flash memory
Methods, apparatuses, and systems for comparing threshold voltages of a plurality of flash memory cells to a plurality of reference voltages. A number of flash...
US-8,077,519 Programming a memory device to increase data reliability
Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be...
US-8,077,518 E/P durability by using a sub-range of a full programming range
A NAND flash memory system is controlled by determining whether to change a value of a voltage threshold. The voltage threshold is associated with an erase...
US-8,077,517 Distributed VDC for SRAM memory
An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A...
US-8,077,516 Method and apparatus for accessing memory with read error by changing comparison
In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code...
US-8,077,515 Methods, devices, and systems for dealing with threshold voltage change in memory devices
The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an...
US-8,077,514 Semiconductor memory device capable of memorizing multivalued data
In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the...
US-8,077,513 Method and apparatus for programming a multi-level memory
A method of programming a memory device comprising a plurality of memory cells may include verifying a first memory cell targeted to a first level with a first...
US-8,077,512 Flash memory cell and method for operating the same
A flash memory cell according to the present invention includes a first charge-trapping region and a second charge-trapping region disposed in a semiconductor...
US-8,077,511 Hybrid non-volatile memory
A non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits...
US-8,077,510 SRAM device
An SRAM device including a memory cell, the memory cell having two access transistors connected to a word line, and a flip-flop circuit having complementary...
US-8,077,509 Magnetic memory
A magnetic memory is provided with a memory cell. The memory cell includes a magnetic recording element, an interconnection to generate a radio-frequency...
US-8,077,508 Dynamic multistate memory write driver
A circuit includes, in part, a multitude of magnetic random access memory cells, one or more column decoders, one or more row decoders, and a write driver...
US-8,077,507 Phase-change memory device
A phase-change memory device includes a data write control unit configured to generate write control signals according to a data combination of a plurality of...
US-8,077,506 Method for programming a multilevel phase change memory device
A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material...
US-8,077,505 Bipolar switching of phase change device
Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a reset bias arrangement to a memory...
US-8,077,504 Shallow trench type quadri-cell of phase-change random access memory (PRAM)
A method of forming a phase-change random access memory (PRAM) cell and PRAM arrangement, and embodiments of phase-change random access memory (PRAM) cells and...
US-8,077,503 Electronic devices utilizing spin torque transfer to flip magnetic orientation
Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure...
US-8,077,502 Electronic devices utilizing spin torque transfer to flip magnetic orientation
Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure...
US-8,077,501 Differential read and write architecture
A memory cell includes a pair of magnetic tunnel junctions and a pair of associated transistors. The magnetic tunnel junctions of the pair are differentially...
US-8,077,500 Volatile memory elements with soft error upset immunity
Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may...
US-8,077,499 Semiconductor integrated memory circuit and trimming method thereof
A latch circuit includes first and second inverters connected in a cross-coupling manner at a first node and a second node. A voltage application circuit...
US-8,077,498 Reading a phase change memory
A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may...
US-8,077,497 Resistive memory device and operating method thereof
A resistive memory device includes: a storage element; a first line and a second line; a first drive controller; and a second drive controller.
US-8,077,496 Nonvolatile memory device and method of driving the same
A nonvolatile memory and a method of driving the same are provided, which adopt an improved write verify operation. The method of driving a nonvolatile memory...
US-8,077,495 Method of programming, erasing and repairing a memory device
A method of programming and erasing a memory device is provided. The memory device includes first and second electrodes and a switching layer therebetween. A...
US-8,077,494 Ferroelectric memory with sub bit-lines connected to each other and to fixed potentials
A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a...
US-8,077,493 Semiconductor memory device
A semiconductor memory device includes a memory cell array disposing a plurality of memory cells at each intersection of word lines and bit lines, the memory...
US-8,077,492 Semiconductor memory device
A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied...
US-8,077,491 Inverter controller
A PWM operation unit includes a modulation-mode selecting unit selecting a two-phase modulation mode signal and a carrier-wave-synchronous-mode select command,...
US-8,077,490 Limit-cycle oscillation (LCO) generation by altering a digital transfer function of a feedback loop element
Limit-cycle oscillation (LCO) generation by altering a digital transfer function of a feedback loop element provides a controllable method and apparatus for...
US-8,077,489 System and method of cancelling noise radiated from a switch-mode power converter
A switch-mode power converter comprises a converter circuit and an auxiliary switching circuit. The converter circuit comprises a storage component configured...
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