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Patent # Description
US-8,078,842 Removing local RAM size limitations when executing software code
An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory...
US-8,078,841 Parsing-enhancement facility using a translate-and-test instruction
An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the...
US-8,078,840 Thread instruction fetch based on prioritized selection from plural round-robin outputs for different thread states
A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch...
US-8,078,839 Concurrent processing element system, and method
An electronic processing element is disclosed for use in a system having a plurality of processing elements. The electronic processing element includes an input...
US-8,078,838 Multiprocessor system having multiport semiconductor memory with processor wake-up function responsive to...
A multiport semiconductor memory device having a processor wake-up function and multiprocessor system, the multiprocessor system including a first processor...
US-8,078,837 Hardware engine control apparatus having hierarchical structure
A hardware engine control apparatus includes: a plurality of hardware engines (HWEs) connected by a control bus, each of the hardware engines executing a series...
US-8,078,836 Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common...
In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a...
US-8,078,835 Reconfigurable array processor for floating-point operations
A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing...
US-8,078,834 Processor architectures for enhanced computational capability
A digital signal processor includes a control block configured to issue instructions based on a stored program, and a compute array including two or more...
US-8,078,833 Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures,...
The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a...
US-8,078,832 Virtual architectures in a parallel processing environment
An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of...
US-8,078,831 Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors
Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread...
US-8,078,830 Processor array accessing data in memory array coupled to output processor with feedback path to input...
An integrated circuit arrangement has a processor array (2) with processor elements (4) and a memory (6) with memory elements (8) arranged in rows (32) and...
US-8,078,829 Scaleable array of micro-engines for waveform processing
A system for implementing waveform processing in a software defined radio (SDR) includes a scaleable array processor having a plurality of micro-engines (MEs)...
US-8,078,828 Memory mapped register file
A method and apparatus for operating a memory mapped register file. The method includes: receiving a source index input having a length of T-1 bits, the source...
US-8,078,827 Method and apparatus for caching of page translations for virtual machines
A method for caching of page translations for virtual machines includes managing a number of virtual machines using a guest page table of a guest operating...
US-8,078,826 Effective memory clustering to minimize page fault and optimize memory utilization
An embodiment of the invention provides a method for effective memory clustering to minimize page faults and optimize memory utilization. More specifically, the...
US-8,078,825 Composite hash and list partitioning of database tables
A method for partitioning during an online node add. The method includes providing a data storage cluster with first and second nodes, and storing a table of...
US-8,078,824 Method for dynamic load balancing on partitioned systems
Methods, systems and apparatuses to dynamically balance execution loads on a partitioned system among processor cores or among partitions.
US-8,078,822 Application independent storage array performance optimizer
A system comprising a performance module and an application. The performance module may be configured to (i) monitor a LUN for a predetermined amount of time,...
US-8,078,821 Semiconductor memory asynchronous pipeline
An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data...
US-8,078,820 Managing message queues
A method, and corresponding system and software, is described for writing data to a plurality of queues, each portion of the data being written to a...
US-8,078,819 Arrangements for managing metadata of an integrated logical unit including differing types of storage media
Network arrangements wherein a network interface receives write requests of files of a file system from a client computer, each file including respective data...
US-8,078,818 Method and system for migrating memory segments
A system comprises a plurality of nodes coupled together via a switching device. Each node comprises a processor coupled to a memory. Migration logic in the...
US-8,078,817 Method and system for secured drive level access for storage arrays
The present disclosure provides a methodology by which disk level access for storage drives of a storage array may be highly secured based on permission...
US-8,078,816 Transparent transfer of qtree and quota metadata in conjunction with logical replication of user data
A technique that provides the ability to copy or move a volume that includes one or more quota structures, by using logical replication, where the volume and...
US-8,078,815 Power-saving-backup management method
A storage subsystem includes: a controller; a first logical storage area corresponding to a RAID group configured by a plurality of storage devices; and a...
US-8,078,814 Method of improving efficiency of replication monitoring
Provided is a copy pair monitoring method which is for a storage system having at least one host computer, at least one storage subsystem, and a management...
US-8,078,813 Triangular asynchronous replication
Storing recovery data includes providing chunks of data to a remote destination, where each chunk of data represents data written before a first time and after...
US-8,078,812 Information terminals sharing contents in a network, information sharing method and P2P system and point system...
Information terminal and information sharing method are provided which consider survival time of contents at a transmission destination and propagate the...
US-8,078,811 Method for digital storage of data on a data memory with limited available storage space
The most important data in a first memory of a data processing system are stored in a limited second data memory given upon a transfer thereof. The demarcation...
US-8,078,810 Storage system and operation method of storage system
The present invention is able to improve the processing performance of a storage system by respectively virtualizing the external volumes and enabling the...
US-8,078,809 System for accessing an offline storage unit through an online storage unit
By the same method as that of making data access to a data storage area in an online state, it is performed to access a data storage area other than the data...
US-8,078,808 Method and device for managing a memory for buffer-storing data blocks in ARQ transmission systems
A data block to be transmitted to a receiver is subjected to channel coding and puncturing in a transmitter. For the purpose of managing data block versions...
US-8,078,807 Accelerating software lookups by using buffered or ephemeral stores
A method and apparatus for accelerating lookups in an address based table is herein described. When an address and value pair is added to an address based...
US-8,078,806 Microprocessor with improved data stream prefetching
A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system...
US-8,078,805 Method and system for communicating with a universal serial bus device
A caching filter driver which is adapted for communicating with a universal serial bus (USB) mass storage device, the caching filter driver is adapted to: (a)...
US-8,078,804 Method and arrangement for cache memory management, related processor architecture
A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data...
US-8,078,803 Apparatus and methods to reduce castouts in a multi-level cache hierarchy
Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the...
US-8,078,802 Method and system for file-system based caching
A method and system for file-system based caching can be used to improve efficiency and security at network sites. In one set of embodiments, the delivery of...
US-8,078,801 Obscuring memory access patterns
For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if...
US-8,078,800 Dynamic operating point modification in an integrated circuit
In one embodiment, an integrated circuit includes a processor, an internal memory, and a memory controller coupled to an external memory. The integrated circuit...
US-8,078,799 Method and system of an adaptive input/output scheduler for storage arrays
An adaptive input/output (I/O) scheduler for storage arrays is disclosed. In one embodiment, a method of a redundant array of independent disks (RAID)...
US-8,078,798 Managing first level storage in a multi-host environment
A virtual tape server (VTS) and a method for managing shared first level storage, such as a disk cache, among multiple virtual tape servers are provided. Such a...
US-8,078,797 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash...
A memory storage system of an embodiment includes a nonvolatile memory unit and memory control circuitry coupled to the memory unit. Storage locations of the...
US-8,078,796 Method for writing to and erasing a non-volatile memory
A method for writing to and erasing a non-volatile memory is described. The method includes determining the size of a command window for use in n write...
US-8,078,795 Methods and media for writing data to flash memory
A method for writing bytes to flash memory is disclosed herein whereby the method comprising includes counting bytes from a data source, the bytes associated...
US-8,078,794 Hybrid SSD using a combination of SLC and MLC flash memory arrays
Hybrid solid state drives (SSD) using a combination of single-level cell (SLC) and multi-level cell (MLC) flash memory arrays are described. According to one...
US-8,078,793 Method, apparatus, and computer-readable medium for storing data on a non-volatile memory device
A non-volatile memory device stores configuration variables for use by a computer firmware. The variable is initially stored in the memory device in a manner...
US-8,078,792 Separate page table base address for minivisor
In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM))....
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