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Patent # Description
US-8,086,942 Parallel concatenated code with bypass
A method of encoding non-key frame data is disclosed. The method includes forming a bit stream from the data by arranging the bits from the data in a known...
US-8,086,941 Computing an error detection code syndrome based on a correction pattern
The present invention is all error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the...
US-8,086,940 Iterative decoding between turbo and RS decoders for improving bit error rate and packet error rate
A technique for iterative decoding between turbo and Reed Solomon (RS) decoders for improving bit error rate (BER) and packet error rate (PER) in a receiver in...
US-8,086,939 XOR circuit, RAID device capable of recovering a plurality of failures and method thereof
An XOR circuit, a RAID device which can recover several failures and method thereof are provided. A Galois field data recovery circuit having two or more sets...
US-8,086,938 Method for processing noise interference
A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in...
US-8,086,937 Method for erasure coding data across a plurality of data stores in a network
An efficient method to apply an erasure encoding and decoding scheme across dispersed data stores that receive constant updates. A data store is a persistent...
US-8,086,936 Performing error correction at a memory device level that is transparent to a memory channel
A memory system is provided that performs error correction at a memory device level that is transparent to a memory channel. The memory system comprises a...
US-8,086,935 Soft error correction for a data storage mechanism
An apparatus and method are disclosed for correcting errors in data obtained from read operations on a storage medium. Errors that occur in a minority of read...
US-8,086,934 Decoding apparatus and decoding method
A decoding apparatus and method are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus...
US-8,086,933 Semiconductor storage device, method of controlling the same, and error correction system
A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without...
US-8,086,932 Apparatus and method for decoding low-density parity check code
There is provided with a decoding apparatus for decoding a low-density parity check code defined by a parity check matrix, includes: a first operation unit...
US-8,086,931 Method and device for multi phase error-correction
Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are...
US-8,086,930 Fixed-spacing parity insertion for FEC (Forward Error Correction) codewords
Fixed-spacing parity insertion for FEC (Forward Error Correction) codewords. Fixed spacing is employed to intersperse parity bits among information bits when...
US-8,086,929 Method of executing LDPC coding using parity check matrix
A low density parity check (LDPC) coding method, and more particularly, a method of executing LDPC coding using a parity check matrix is disclosed. The present...
US-8,086,928 Methods and systems for terminating an iterative decoding process of a forward error correction block
The invention provides methods and systems for terminating an iterative decoding process of a Forward Error Correction block (FEC). The iterative decoding...
US-8,086,927 MIMO transmitting apparatus, MIMO receiving apparatus, and retransmitting method
A MIMO transmitting apparatus that achieves a flexible control in accordance with variation of a propagation environment to reduce the number of retransmissions...
US-8,086,926 Failure diagnostic apparatus, failure diagnostic system, and failure diagnostic method
There is provided a failure diagnostic apparatus that diagnoses a semiconductor integrated circuit device for failure based on a compressed signal obtained by...
US-8,086,925 Method and system for LBIST testing of an electronic circuit
A method for testing an electronic circuit comprises selecting a first log interval, a first log start pattern, a first log end pattern, and a first subset...
US-8,086,924 Implementing diagnosis of transitional scan chain defects using logic built in self test LBIST test patterns
A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In...
US-8,086,923 Accurately identifying failing scan bits in compression environments
X-masking registers are added in front of a compactor in test data compression environment to remove unknown values. The X-masking registers block out some...
US-8,086,922 Programmable logic device with differential communications support
Programmable logic device integrated circuits with differential communications circuitry are provided in which the differential communications circuitry is used...
US-8,086,921 System and method of clocking an IP core during a debugging operation
According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock...
US-8,086,920 Method of controlling a test mode of a circuit
A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an...
US-8,086,919 Controller having flash memory testing functions, and storage system and testing method thereof
A flash memory controller having a flash memory testing functions is provided, in which the flash memory controller includes a microprocessor unit, a flash...
US-8,086,918 High-speed serial transfer device test data storage medium and device
A test pattern generating unit generates a test pattern in which unconverted data is arranged such that same values of 0 or 1 bits in converted data according...
US-8,086,917 Methods for characterizing device variation in electronic memory circuits
A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its...
US-8,086,916 System and method for running test and redundancy analysis in parallel
A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different...
US-8,086,915 Memory controller with loopback test interface
In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the...
US-8,086,914 Storing data to multi-chip low-latency random read memory device using non-aligned striping
Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device...
US-8,086,913 Methods, apparatus, and systems to repair memory
Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could...
US-8,086,912 Monitoring and root cause analysis of temporary process wait situations
A computing system is provided and includes first computing resources representing a fraction of total computing resources, second computing resources...
US-8,086,911 Method and apparatus for distributed reconstruct in a raid system
Embodiments of the present invention provide techniques for distributing the reconstruction process of a failed storage device in an array of storage devices to...
US-8,086,910 Monitoring software thread execution
The invention is directed to monitoring execution of software threads, particularly by detecting a lockup or stall in execution of a software thread and...
US-8,086,909 Automatic core file upload
A support center receives an error message from a remote storage system indicating that an error, such as a kernel panic, has occurred on the remote storage...
US-8,086,908 Apparatus and a method for reporting the error of each level of the tunnel data packet in a communication network
The invention provides methods and devices for reporting and parsing the errors of a packet based on IPSec protocol family in a communication network....
US-8,086,907 Systems and methods for network information collection
A network device may include logic configured to receive a problem report from a second network device, store and analyze data included in the problem report,...
US-8,086,906 Correlating hardware devices between local operating system and global management entity
A method and apparatus for correlating the identities of hardware devices, such as processors and memory controllers, between a local operating system and a...
US-8,086,905 Method of collecting information in system network
To quickly establish an inferring result when a problem is detected in an operation management system equipped with a rule-based inference processing function,...
US-8,086,904 Event-based setting of process tracing scope
Detecting an anomaly is disclosed. An indication that a computer system monitoring instrument is desired to provide as output a subset of the output data that...
US-8,086,903 Method, apparatus, and computer program product for coordinating error reporting and reset utilizing an I/O...
A method, apparatus, and computer program product are disclosed in a shared processor data processing system for coordinating error reporting for and resetting...
US-8,086,902 Method and apparatus for testing media player software applications
A method, system and program application is provided for automatically testing the operation of a media player with media files (e.g., video files) that are...
US-8,086,901 Timer circuit and timer method
A timer circuit and a timer method are provided for a BIOS of an electronic device. The timer circuit includes a processing module, a setting module, and a...
US-8,086,900 System, method and computer program product for testing a boot image
According to one embodiment of the present disclosure, a method for testing a boot image is disclosed. The method comprises creating a test boot image for a...
US-8,086,899 Diagnosis of problem causes using factorization
Technology is described for diagnosing problem causes in complex environments by using factorization of a plurality of features. An embodiment can include the...
US-8,086,898 Redundant I/O module
A redundant I/O module includes: a control I/O module that communicates with a controller and that comprises a first IOM setting information holding section for...
US-8,086,897 Model driven diagnostics system and methods thereof
A method to perform a diagnostic test in an integrated support platform having a plurality of services is disclosed. The method includes a process of building...
US-8,086,896 Dynamically tracking virtual logical storage units
In virtualized environments, storage may be managed dynamically due to the changing data storage requirements. In such environments, logical storage unit...
US-8,086,895 Management method and system for managing replication by taking into account cluster storage accessibility a...
A management system, which manages a host computer and a storage system, holds cluster information, specifies an active-state host computer and an ...
US-8,086,894 Managing redundant network components
A method for managing redundant network components is disclosed. A network component operable to perform in an active mode is monitored. The network component...
US-8,086,893 High performance pooled hot spares
A high-performance spare disk pool is created as a logical construct for provisioning and managing striped hot spares. Two or more drives (nonvolatile mass...
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