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Patent # Description
US-8,084,879 Wind turbine
The invention concerns a wind turbine comprising a retaining arrangement, a main shaft and a direct drive generator comprising a rotor having a first and a...
US-8,084,878 Fluid powered energy generator
A power plant with one or more fluid operated generator unit(s) is provided to generate electrical energy. Each generator unit includes one or more rotational...
US-8,084,877 Methods and devices for converting wave energy into rotational energy
The invention discloses devices and methods for converting wave energy to rotational energy. Specifically, the invention allows for two or more flotation...
US-8,084,876 Use of oriented grain rolling in a wind turbine generator
The present invention relates to a wind turbine for generating electric power. The wind turbine includes a generator (105) and a wind turbine rotor (101) for...
US-8,084,875 Wind energy installation with an extended rotation speed range
A wind energy installation includes a wind rotor, a double-fed asynchronous generator driven by the wind rotor, a converter provided with a first part on the...
US-8,084,874 Method of maintaining wind turbine components operational and a turbine comprising components suitable for...
The invention relates to a wind turbine (1) which is connected to an electrical power grid (23) and which uses a magnet generator (6) as the only electrical...
US-8,084,873 Induced surface flow wave energy converter
A wave energy conversion device that employs a submerged horizontally-aligned structure provided with a central opening formed in a horizontally extending...
US-8,084,872 Overlay mark, method of checking local aligmnent using the same and method of controlling overlay based on the same
An overlay mark is described, including N sets of parallel x-directional linear patterns respectively defined by N (.gtoreq.2) exposure steps and N sets of...
US-8,084,871 Redistribution layer enhancement to improve reliability of wafer level packaging
An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level...
US-8,084,870 Semiconductor devices and electrical parts manufacturing using metal coated wires
The device of this invention includes a semiconductor die attached to a bare copper lead frame and electrically coupled to a lead by a metal wire coated with a...
US-8,084,869 Semiconductor device and method for manufacturing the same
A technique permitting the reduction in size of a semiconductor device is provided. In a BGA type semiconductor device with a semiconductor chip ...
US-8,084,868 Semiconductor package with fast power-up cycle and method of making same
In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including at least two electronic components which...
US-8,084,867 Apparatus, system, and method for wireless connection in integrated circuit packages
Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of...
US-8,084,866 Microelectronic devices and methods for filling vias in microelectronic devices
Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one...
US-8,084,865 Anchoring structure and intermeshing structure
An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the...
US-8,084,864 Electromigration resistant aluminum-based metal interconnect structure
A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is...
US-8,084,863 Circuitized substrate with continuous thermoplastic support film dielectric layers
A circuitized substrate including a dielectric layer having a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin and not including...
US-8,084,862 Interconnect structures with patternable low-k dielectrics and method of fabricating same
The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically,...
US-8,084,861 Connection structure semiconductor chip and electronic component including the connection structure and methods...
Connection structure (5) for attaching a semiconductor chip (2) to a metal substrate (4) is provided which has a plurality of electrically conducting layers...
US-8,084,860 Liquid crystal display device and manufacturing method therefor
The present invention includes a liquid crystal display device having an oxide film having high adhesiveness to a substrate to thereby prevent oxidation of a...
US-8,084,859 Semiconductor device
In a wafer level CSP package, with respect to signal wiring 9b disposed in a signal wiring disposition forbidden region 16 in the vicinity of external output...
US-8,084,858 Metal wiring structures for uniform current density in C4 balls
In one embodiment, a sub-pad assembly of metal structures is located directly underneath a metal pad. The sub-pad assembly includes an upper level metal line...
US-8,084,857 Method and article of manufacture for wire bonding with staggered differential wire bond pairs
A method and article of manufacture for performing wire-bonding operations in an integrated circuit. In one aspect, the operations include the steps of bonding...
US-8,084,856 Thermal spacer for stacked die package thermal management
In some embodiments, a thermal spacer for stacked die package thermal management is presented. In this regard, an apparatus is introduced having a top...
US-8,084,855 Integrated circuit tampering protection and reverse engineering prevention coatings and methods
A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic...
US-8,084,854 Pass-through 3D interconnect for microelectronic dies and associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a...
US-8,084,853 Semiconductor flip chip package utilizing wire bonding for net switching
This invention provides a semiconductor flip chip package including a carrier substrate and a flip chip mounted on the carrier substrate. The flip chip...
US-8,084,852 Hybrid integrated circuit device, and method for fabricating the same, and electronic device
A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic...
US-8,084,851 Side stacking apparatus and method
A module has at least two ICs connected to each other such that they lie in different planes and are arranged as a first stack of ICs, a third IC is connected...
US-8,084,850 Semiconductor chip package, stacked package comprising semiconductor chips and methods of fabricating chip and...
According to an example embodiment, a semiconductor chip package includes a substrate comprising a substrate body having a first main surface, a second main...
US-8,084,849 Integrated circuit package system with offset stacking
An integrated circuit package system includes: providing an interposer having a bond pad and a contact pad; mounting the interposer in an offset location over a...
US-8,084,848 Leadframe, leadframe type package and lead lane
A leadframe for a leadframe type package includes a chip base, and leads constituting lead lanes. One lead lane includes a pair of first differential signal...
US-8,084,847 Prefabricated lead frame and bonding method using the same
A prefabricated lead frame to bond a chip and a substrate, and a bonding method using the prefabricated lead frame. The prefabricated lead frame includes an...
US-8,084,846 Balanced semiconductor device packages including lead frame with floating leads and associated methods
A semiconductor device assembly or package includes at least one semiconductor device that is positioned adjacent to floating leads. Such an assembly or package...
US-8,084,845 Subresolution silicon features and methods for forming the same
Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and...
US-8,084,844 Semiconductor device
A semiconductor device in which potential is uniformly controlled and in which the influence of noise is reduced. A p-type well region is formed beneath a...
US-8,084,843 N well implants to separate blocks in a flash memory device
A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is...
US-8,084,842 Thermally stabilized electrode structure
Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a first electrode layer, a second electrode...
US-8,084,841 Systems and methods for providing high-density capacitors
The present invention describes systems and methods for providing high-density capacitors. An exemplary embodiment of the present invention provides a...
US-8,084,840 Interposer including air gap structure, methods of forming the same, semiconductor device including the...
Example embodiments of the present invention relate to an interposer of a semiconductor device having an air gap structure, a semiconductor device using the...
US-8,084,839 Circuit board having conductive shield member and semiconductor package using the same
A circuit board having a board body includes a via structure. The via structure includes a conductive connector passing through the board body and a conductive...
US-8,084,838 Large-area PIN diode with reduced capacitance
The invention provides a design of PIN diode having a low capacitance and a large area of effective collection of photo-generated charge. The low capacitance is...
US-8,084,837 Solid-state image pickup device
In a rear surface incidence type CMOS image sensor having a wiring layer 720 on a first surface (front surface) of an epitaxial substrate 710 in which a...
US-8,084,836 Semiconductor photodetector and radiation detecting apparatus
A photodiode array PD1 comprises an n-type semiconductor substrate one face of which is an incident surface of light to be detected; a plurality of pn...
US-8,084,835 Non-uniform switching based non-volatile magnetic based memory
A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer...
US-8,084,834 Semiconductor device and method for manufacturing same
A semiconductor device of the present invention includes: a semiconductor layer; a gate insulation film provided on the semiconductor layer and including at...
US-8,084,833 Semiconductor device
Provided is a LOCOS offset MOS field-effect transistor in which a first lightly-doped N-type drain offset region with a LOCOS oxide film and a second...
US-8,084,832 Semiconductor device
Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of...
US-8,084,831 Semiconductor device
A semiconductor device according to one embodiment includes: an n-type transistor comprising a first gate electrode formed on a semiconductor substrate via a...
US-8,084,830 Nonvolatile semiconductor memory device
The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a...
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