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Patent # Description
US-8,084,325 Semiconductor device and method for fabricating the same
A semiconductor device can prevent exposure of an inner wall of a recess pattern caused by misalignment between masks. A gate electrode is formed inside the...
US-8,084,324 Nonvolatile semiconductor memory and fabrication method for the same
A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating...
US-8,084,323 Stack capacitor of memory device and fabrication method thereof
The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a...
US-8,084,322 Method of manufacturing devices having vertical junction edge
Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled...
US-8,084,321 DRAM cell with enhanced capacitor area and the method of manufacturing the same
A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor....
US-8,084,320 Non-volatile memory and method for fabricating the same
A non-volatile memory is described, which includes gate structures, doped regions, second spacers and contact plugs. The gate structures are disposed on the...
US-8,084,319 Precisely tuning feature sizes on hard masks via plasma treatment
Methods are provided for fabricating devices. A first layer is formed. A hardmask on the first layer is formed. Features on the hardmask are patterned. The...
US-8,084,318 Methods of fabricating integrated circuit devices including strained channel regions and related devices
A method of fabricating an integrated circuit device includes forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS...
US-8,084,317 Semiconductor device and method of manufacturing the same
Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a gate electrode on a semiconductor substrate...
US-8,084,316 Method of fabricating single transistor floating-body DRAM devices having vertical channel transistor structures
Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating...
US-8,084,315 Method of fabricating non-volatile semiconductor memory device by using plasma film-forming method and plasma...
A technique capable of improving the memory retention characteristics of a non-volatile memory is provided. In particular, a technique of fabricating a...
US-8,084,314 Semiconductor device and manufacturing method thereof
A first insulation film is provided on a semiconductor substrate. A high resistance element formed from polysilicon is provided on the first insulation film. A...
US-8,084,313 Method for forming a bipolar junction transistor and a metal oxide semiconductor field effect transistor
A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices...
US-8,084,312 Nitrogen based implants for defect reduction in strained silicon
A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain...
US-8,084,311 Method of forming replacement metal gate with borderless contact and structure thereof
Embodiments of the present invention provide a method of forming borderless contact for transistor in a replacement metal gate process. The method includes...
US-8,084,310 Self-aligned multi-patterning for advanced critical dimension contacts
Embodiments of the present invention pertain to methods of forming patterned features on a substrate having a reduced pitch in two dimensions as compared to...
US-8,084,309 Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped...
A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI...
US-8,084,308 Single gate inverter nanowire mesh
Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers...
US-8,084,307 Method for manufacturing thin film transistor
A method for manufacturing a thin film transistor containing an channel layer 11 having indium oxide, including forming an indium oxide film as an channel layer...
US-8,084,306 Methods of forming semiconductor devices having self-aligned bodies
A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain...
US-8,084,305 Isolation spacer for thin SOI devices
A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation...
US-8,084,304 Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD...
A method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET includes...
US-8,084,303 Semiconductor device and a method of manufacturing the same
In a memory cell array on a main surface of a semiconductor substrate, a floating gate electrode for accumulating charges for information is arranged. The...
US-8,084,302 Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor
A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate,...
US-8,084,301 Resin sheet, circuit device and method of manufacturing the same
Provided is a circuit device manufacturing method for coating a bottom surface of a circuit board with a thin coating of sealing resin. In the present...
US-8,084,300 RF shielding for a singulated laminate semiconductor device package
A method for manufacturing a semiconductor device package to provide RF shielding. The device is mounted on a laminated substrate having conducting pads on its...
US-8,084,299 Semiconductor device package and method of making a semiconductor device package
A method of manufacturing an electronic device is provided. The method comprises providing a carrier sheet, etching the lead frame material sheet to form a...
US-8,084,298 Method for exchanging semiconductor chip of flip-chip module and flip-chip module suitable therefor
A process for replacing a semiconductor chip of such a flip-chip module and a suitable flip-chip module and an apparatus for implementing the method are...
US-8,084,297 Method of implementing a capacitor in an integrated circuit
A method of implementing a capacitor in an integrated circuit package is disclosed. The method comprises coupling the capacitor to a first surface of a...
US-8,084,296 Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods
Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One such device can include a...
US-8,084,295 Thin film transistor having n-type and p-type CIS thin films and method of manufacturing the same
Provided is a thin film transistor (TFT) which uses CIS (CuInSe.sub.2), including Se, which is a chalcogen-based material, and can provide a rectifying...
US-8,084,294 Method of fabricating organic silicon film, semiconductor device including the same, and method of fabricating...
An organic silicon film is formed by carrying out chemical vapor deposition with organic silicon compound being used as a raw material gas. The organic silicon...
US-8,084,293 Continuously optimized solar cell metallization design through feed-forward process
An improved, lower cost method of processing substrates, such as to create solar cells, is disclosed. The doped regions are created on the substrate, using a...
US-8,084,292 Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass...
The thermal management and method for large scale processing of CIS and/or CIGS based thin film overlaying glass substrates. According to an embodiment, the...
US-8,084,291 Thermal management and method for large scale processing of CIS and/or CIGS based thin films overlying glass...
The thermal management and method for large scale processing of CIS and/or CIGS based thin film overlaying glass substrates. According to an embodiment, the...
US-8,084,290 Method for fabricating CMOS image sensor
A method of forming a CMOS image sensor and a CMOS image sensor. A method of forming a CMOS image sensor may include forming a plurality of photodiodes on...
US-8,084,289 Method of fabricating image sensor and reworking method thereof
A method of fabricating an image sensor device is provided. First, a substrate comprising a pixel array region and a pad region is provided. A patterned metal...
US-8,084,288 Method of construction of CTE matching structure with wafer processing and resulting structure
A method includes bonding a first side of a metal shim to a silicon shim, removing metal from the metal shim to form a plurality of cleared metal lanes in...
US-8,084,287 Photoelectric conversion apparatus, producing method therefor, image pickup module and image pickup system
A photoelectric conversion apparatus has a plurality of photoelectric conversion elements arranged on a semiconductor substrate, a plurality of wiring layers...
US-8,084,286 Solid-state imaging device, camera and method of producing the solid-state imaging device
Producing a solid-state imaging device by (1) forming a structure including (a) a substrate having a first impurity with a first concentration, (b) a first...
US-8,084,285 Forming a micro electro mechanical system
A method of forming a micro-electro mechanical system (MEMS), includes (1) removing material from a first wafer to define a first movable portion corresponding...
US-8,084,284 Complementary metal oxide semiconductor image sensor and method for fabricating the same
A complementary metal oxide semiconductor (CMOS) device and a method for fabricating the same are provided. The CMOS image sensor includes: a first conductive...
US-8,084,283 Top contact LED thermal management
An LED having enhanced heat dissipation is disclosed. For example, an LED die can have extended bond pads that are configured to enhance heat flow from an...
US-8,084,282 Wafer-level In-P Si bonding for silicon photonic apparatus
Wafer-level bonding of the hybrid laser portion of a silicon photonics platform is done by forming a weakened level in a semiconductive pillar that supports...
US-8,084,281 Semiconductor substrate, electronic device, optical device, and production methods therefor
The present invention provides a method for producing a semiconductor substrate, the method including reacting nitrogen (N) with gallium (Ga), aluminum (Al), or...
US-8,084,280 Method of manufacturing a solar cell using a pre-cleaning step that contributes to homogeneous texture morphology
A method of manufacturing a solar cell wherein a pre-cleaning step is completed prior to a saw damage removal step and prior to texturization, thereby resulting...
US-8,084,279 Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for...
According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift...
US-8,084,278 Method of manufacturing silicon carbide semiconductor device
A wafer WF is mounted in a substrate holder, and the substrate holder is placed in a film forming furnace. The film forming furnace is evacuated by a vacuum...
US-8,084,277 Semiconductor device and manufacturing method thereof
A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to...
US-8,084,276 Method for identifying a subject at risk of developing heart failure by determining the level of galectin-3 or...
Described herein are methods for identifying a subject at risk of progression of heart failure. In some embodiments, the level of galectin-3 in a biological...
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