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| Patent # | Description |
|---|---|
| US-8,110,508 |
Method of forming a bump structure using an etching composition for an
under bump metallurgy layer In an etching composition for an under-bump metallurgy (UBM) layer and a method of forming a bump structure, the etching composition includes about 40% by... |
| US-8,110,507 |
Method for patterning an active region in a semiconductor device using a
space patterning process Disclosed here in is a method for patterning an active region in a semiconductor device using a space patterning process that includes forming a partition... |
| US-8,110,506 |
Methods of forming fine patterns in semiconductor devices Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning,... |
| US-8,110,505 |
Lead frame manufactured from low-priced material and not requiring strict
process control, semiconductor... Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die... |
| US-8,110,504 |
Method of manufacturing semiconductor device The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer... |
| US-8,110,503 |
Surface preparation for thin film growth by enhanced nucleation Various processes and related systems are provided for making structures on substrate surfaces. Disclosed are methods of making a structure supported by a... |
| US-8,110,502 |
Method of improving adhesion strength of low dielectric constant layers A method for manufacturing a semiconductor device is provided. In a specific embodiment, the method includes providing a semiconductor substrate with a surface... |
| US-8,110,501 |
Method of fabricating landing plug with varied doping concentration in
semiconductor device A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor... |
| US-8,110,500 |
Mitigation of plating stub resonance by controlling surface roughness Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases... |
| US-8,110,499 |
Method of forming a contact structure An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact... |
| US-8,110,498 |
Method for passivating exposed copper surfaces in a metallization layer of
a semiconductor device When forming sophisticated metallization systems, surface integrity of an exposed metal surface, such as a copper-containing surface, may be enhanced by... |
| US-8,110,497 |
Method for manufacturing semiconductor device An embodiment of the present invention provides a method for manufacturing a semiconductor device. This method comprises: forming a seed film at least on an... |
| US-8,110,496 |
Method for performing chemical shrink process over BARC (bottom
anti-reflective coating) A structure and a method for forming the same. The method comprises providing a structure including (a) a hole layer, (b) a BARC (bottom antireflective coating)... |
| US-8,110,495 |
Multilayer wiring structure of semiconductor device, method of producing
said multilayer wiring structure and... A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the... |
| US-8,110,494 |
Systems and methods for maximizing breakdown voltage in semiconductor
devices Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between... |
| US-8,110,493 |
Pulsed PECVD method for modulating hydrogen content in hard mask A method for forming a PECVD deposited amorphous carbon or ashable hard mask (AHM) in a trench or a via with less than 30% H content at a process temperature... |
| US-8,110,492 |
Method for connecting a die attach pad to a lead frame and product thereof Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one... |
| US-8,110,491 |
Method of manufacturing semiconductor device and substrate processing
apparatus A manufacturing method of a semiconductor device of the present invention includes the step of forming an insulating film on a substrate, and the step of... |
| US-8,110,490 |
Gate oxide leakage reduction A method of manufacturing a semiconductor device comprising forming a gate oxide layer over a substrate subjecting the gate oxide layer to a first nitridation... |
| US-8,110,489 |
Process for forming cobalt-containing materials Embodiments of the invention described herein generally provide methods and apparatuses for forming cobalt silicide layers, metallic cobalt layers, and other... |
| US-8,110,488 |
Method for increasing etch rate during deep silicon dry etch A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of... |
| US-8,110,487 |
Method of creating a strained channel region in a transistor by deep
implantation of strain-inducing species... By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient... |
| US-8,110,486 |
Method of manufacturing semiconductor wafer by forming a strain relaxation
SiGe layer on an insulating layer of... A semiconductor wafer is produced at a step of forming a lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer on an insulating layer in a... |
| US-8,110,485 |
Nanocrystal silicon layer structures formed using plasma deposition
technique, methods of forming the same,... Provided are nanocrystal silicon layer structures formed using a plasma deposition technique, methods of forming the same, nonvolatile memory devices including... |
| US-8,110,484 |
Conductive nitride semiconductor substrate and method for producing the
same A method for producing a conductive nitride semiconductor substrate circuit includes the steps of forming, on an underlying substrate, a mask including dot or... |
| US-8,110,483 |
Forming an extremely thin semiconductor-on-insulator (ETSOI) layer Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including... |
| US-8,110,482 |
Miscut semipolar optoelectronic device A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises... |
| US-8,110,481 |
Method of segmenting semiconductor wafer To provide a method of segmenting a semiconductor wafer, which is capable of preventing chippings. A semiconductor wafer 1 is partitioned into a circumferential... |
| US-8,110,480 |
Method and structure for fabricating solar cells using a thick layer
transfer process A photovoltaic cell device, e.g., solar cell, solar panel, and method of manufacture. The device has an optically transparent substrate comprises a first... |
| US-8,110,479 |
Manufacturing method of SOI substrate provided with barrier layer To provide a method for manufacturing a large-area semiconductor device, to provide a method for manufacturing a semiconductor device with high efficiency, and... |
| US-8,110,478 |
Method for manufacturing semiconductor substrate, display panel, and
display device If the size of a single crystal silicon layer attached is not appropriate, even when a large glass substrate is used, the number of panels to be obtained cannot... |
| US-8,110,477 |
Semiconductor device and method of forming high-frequency circuit
structure and method thereof A semiconductor device is made by providing an integrated passive device (IPD). Through-silicon vias (TSVs) are formed in the IPD. A capacitor is formed over a... |
| US-8,110,476 |
Memory cell that includes a carbon-based memory element and methods of
forming the same In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate,... |
| US-8,110,475 |
Method for forming a memory device with C-shaped deep trench capacitors The invention is related to a memory device, including a substrate, a capacitor which is substantially C-shaped in a cross section parallel to the substrate... |
| US-8,110,474 |
Method of making micromodules including integrated thin film inductors Micromodules and methods of making them are disclosed. An exemplary micromodule includes a substrate having a thin film inductor, and a bumped die mounted on... |
| US-8,110,473 |
Semiconductor device comprising multilayer dielectric film and related
method A semiconductor device including a multilayer dielectric film and a method for fabricating the semiconductor device are disclosed. The multilayer dielectric... |
| US-8,110,472 |
High power and high temperature semiconductor power devices protected by
non-uniform ballasted sources A semiconductor power device is formed on a semiconductor substrate. The semiconductor power device includes a plurality of transistor cells distributed over... |
| US-8,110,471 |
Semiconductor device having a round-shaped nano-wire transistor channel
and method of manufacturing same A field-effect transistor (FET) with a round-shaped nano-wire channel and a method of manufacturing the FET are provided. According to the method, source and... |
| US-8,110,470 |
Asymmetrical transistor device and method of fabrication Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel... |
| US-8,110,469 |
Graded dielectric layers Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of... |
| US-8,110,468 |
DMOS-transistor having improved dielectric strength of drain and source
voltages A DMOS-transistor having enhanced dielectric strength includes a first well region. A highly doped source region is located in the first well region and is... |
| US-8,110,467 |
Multiple Vt field-effect transistor devices Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is... |
| US-8,110,466 |
Cross OD FinFET patterning A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask,... |
| US-8,110,465 |
Field effect transistor having an asymmetric gate electrode The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that... |
| US-8,110,464 |
SOI protection for buried plate implant and DT bottle ETCH An SOI layer has an initial trench extending therethrough, prior to deep trench etch. An oxidation step, such as thermal oxidation is performed to form a band... |
| US-8,110,463 |
Method of fabricating semiconductor device A method of fabricating a semiconductor device includes a first step of forming a defect suppression film suppressing increase in a defect due to implantation... |
| US-8,110,462 |
Reduced finger end MOSFET breakdown voltage (BV) for electrostatic
discharge (ESD) protection The present invention relates to electrostatic discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more... |
| US-8,110,461 |
Flash memory device and manufacturing method of the same Disclosed are a flash memory device and a method for manufacturing the same. The flash memory device includes first and second memory gates on a substrate; a... |
| US-8,110,460 |
Method for producing stacked and self-aligned components on a substrate A method for producing stacked and self-aligned components on a substrate, including: providing a substrate made of monocrystalline silicon having one face... |
| US-8,110,459 |
MOSFET having a channel region with enhanced stress and method of forming
same A semiconductor device is provided that includes a semiconductor substrate, an n-channel MOSFET formed on the substrate and a p-channel MOSFET formed on the... |
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