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Patent # Description
US-8,129,806 Magnetic memory device
A magnetic memory device includes a magnetic tunnel junction (MTJ) structure and an electrode embedded in a dielectric structure. The MTJ structure includes a...
US-8,129,805 Microelectromechanical system (MEMS) device and methods for fabricating the same
A method of fabricating a microelectromechanical system (MEMS) device includes providing a semiconductor substrate having a semiconductor layer and an...
US-8,129,804 Electronic device, resonator, oscillator and method for manufacturing electronic device
An electronic device includes a substrate, a functional structural body formed on the substrate and a covering structure for defining a cavity part having the...
US-8,129,803 Micromachined microphone and multisensor and method for producing same
A micromachined microphone is formed from a silicon or silicon-on-insulator (SOI) wafer. A fixed sensing electrode for the microphone is formed from a top...
US-8,129,802 Integrated micro electro-mechanical system and manufacturing method thereof
In the manufacturing technology of an integrated MEMS in which a semiconductor integrated circuit (CMOS or the like) and a micro machine are monolithically...
US-8,129,801 Discrete stress isolator attachment structures for MEMS sensor packages
A discrete stress isolation apparatus for a Micro Electro-Mechanical System (MEMS) inertial sensor device having a mechanism die and a package. A capacitive...
US-8,129,800 Gate-all-around integrated circuit devices
Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and...
US-8,129,799 Semiconductor device
A field-effect transistor (142) includes a lowly p-doped region 110 formed on a surface of a substrate (102), an n-doped drain region 112 and n-doped source...
US-8,129,798 Semiconductor device comprising fully-depleted and partially-depleted FinFETs
A semiconductor device includes a circuit comprising a first transistor in a first Fin; a power supply circuit in a second Fin, the power supply circuit...
US-8,129,797 Work function engineering for eDRAM MOSFETs
Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1)...
US-8,129,796 Semiconductor device
There is provided a high-integrated complementary metal-oxide semiconductor static random-access memory including an inverter. The inverter includes: a first...
US-8,129,795 Inducing strain in the channels of metal gate transistors
In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher...
US-8,129,794 Semiconductor device including MISFETs having different threshold voltages
A semiconductor device includes a first MIS transistor, and a second MIS transistor having a threshold voltage higher than that of the first MIS transistor. The...
US-8,129,793 Semiconductor integrated device and manufacturing method for the same
A first exemplary aspect of an exemplary embodiment of the present invention is a semiconductor integrated device comprising a semiconductor substrate, a first...
US-8,129,792 Semiconductor device and method for manufacturing the same
A semiconductor device includes n- and p-type semiconductor regions separately formed on a substrate, an interlayer insulator formed on the substrate and having...
US-8,129,791 Semiconductor device having a contact plug and manufacturing method thereof
There is provided a semiconductor device that includes: a transistor having a gate electrode, a source region, and a drain region; a first inter-layer...
US-8,129,790 HOT process STI in SRAM device and method of manufacturing
A structure and method for forming SRAMs on HOT substrates with STI is described. Logic circuits may also be fabricated on the same chip with some devices on...
US-8,129,789 Current control using thermally matched resistors
A semiconductor chip includes a semiconductor body having an upper surface. At least one power semiconductor component is integrated in the semiconductor chip...
US-8,129,788 Capacitor triggered silicon controlled rectifier
A protection circuit and method are provided for protecting semiconductor devices from electrostatic discharge (ESD). Generally, the ESD protection circuit...
US-8,129,787 Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink
A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and...
US-8,129,785 Semiconductor device
A semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; an annular deep trench penetrating the...
US-8,129,784 Semiconductor device
The invention improves the performance of a semiconductor device. A metal silicide film is formed by a silicide process on a gate electrode and an n.sup.+-type...
US-8,129,783 Lateral power MOSFET with high breakdown voltage and low on-resistance
A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of...
US-8,129,782 High-voltage transistor and method for its manufacture
A high-voltage transistor is provided with a well of a first conductivity type, which is arranged in a substrate (10) of a second conductivity type, with a...
US-8,129,781 Method of forming memory devices by performing halogen ion implantation and diffusion processes
Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes...
US-8,129,780 Semiconductor device having a trench type high-power MISFET
The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a...
US-8,129,779 Trench gate type VDMOSFET device with thicker gate insulation layer portion for reducing gate to source capacitance
A semiconductor device according to the present invention includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of...
US-8,129,778 Semiconductor devices and methods for making the same
Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices...
US-8,129,777 Semiconductor device having a multi-channel type MOS transistor
In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate...
US-8,129,776 Semiconductor device
A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a...
US-8,129,775 Semiconductor device and method of manufacturing the same
The semiconductor device has a stacked structure in which a tunnel oxide layer, a charge trapping layer, a blocking oxide layer, and a gate electrode are...
US-8,129,774 EEPROM with increased reading speed
In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage V.sub.read of the memory cell in a...
US-8,129,773 Fin-type field effect transistor
Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment...
US-8,129,772 Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact
Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These...
US-8,129,771 Semiconductor memory device
In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer...
US-8,129,770 Semiconductor device and manufacturing method thereof
A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode...
US-8,129,769 Semiconductor device and manufacturing method thereof
A semiconductor device having a 6F.sup.2 memory cell whose size is defined by a numerical value of a design rule F, wherein: lower electrodes of capacitors...
US-8,129,768 Integrated circuit device, manufacturing method thereof, and display device
An integrated circuit device of the present invention includes a substrate on which at least two types of nano wire element are provided. These nano wire...
US-8,129,767 Ferroelectric polymer memory module
Ferroelectric polymer memory modules are described. In an example, a module has a first set of layers including a first ILD layer defining trenches therein, a...
US-8,129,766 Semiconductor memory device comprising shifted contact plugs
A memory includes first contact plugs; ferroelectric capacitors above the first contact plugs; second contact plugs in a first interlayer film being below an...
US-8,129,765 CMOS image sensor with photo-detector protecting layers
An image sensor includes a logic region and an APS region having a first gate electrode, a photo-detector, a first protecting layer, first spacers, and a second...
US-8,129,764 Imager devices having differing gate stack sidewall spacers, method for forming such imager devices, and...
Imager devices have a sensor array and a peripheral region at least partially surrounding the sensor array. At least one transistor in the peripheral region has...
US-8,129,763 Metal-oxide-semiconductor device including a multiple-layer energy filter
A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second...
US-8,129,762 Image sensor
A method is provided for processing a substrate. The substrate has at least one filter region, a plurality of bond pads, and a plurality of scribe lines...
US-8,129,761 Contacts for CMOS imagers and method of formation
Low leakage contacts on leakage sensitive areas of a CMOS imager, such as a floating diffusion region or a photodiode, are disclosed. At least one low leakage...
US-8,129,760 Image sensor and image reading apparatus
A structure which meets a high-quality reading requirement and realizes high-speed color reading when the reading section of a color image forming apparatus...
US-8,129,759 Semiconductor package and method using isolated V.sub.SS plane to accommodate high speed circuitry ground isolation
Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached...
US-8,129,758 Semiconductor element and manufacturing method therefor
A semiconductor device includes: a semiconductor layer including silicon carbide, which has been formed on a substrate; a semiconductor region 15 of a first...
US-8,129,757 Integrated circuit including at least six linear-shaped conductive structive structures at equal pitch...
A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a...
US-8,129,756 Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of...
A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell...
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