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Patent # Description
US-8,129,252 Semiconductor devices with sealed, unlined trenches and methods of forming same
A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction...
US-8,129,251 Metal-insulator-metal-structured capacitor formed with polysilicon
A METAL-INSULATOR-METAL structured capacitor is formed with polysilicon instead of an oxide film as a sacrificial layer material that defines a storage...
US-8,129,250 Resistor with improved switchable resistance and non-volatile memory device
A resistor with improved switchable resistance and a non-volatile memory device includes a first electrode, a second electrode facing the first electrode and a...
US-8,129,249 Integrated transistor, particularly for voltages and method for the production thereof
Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating...
US-8,129,248 Method of producing bipolar transistor structures in a semiconductor process
In the method of producing bipolar transistor structures in a semiconductor process, an advanced epitaxial trisilane process can be used without the risk of...
US-8,129,247 Omega shaped nanowire field effect transistors
A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on...
US-8,129,246 Advanced CMOS using super steep retrograde wells
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer...
US-8,129,245 Methods of manufacturing power semiconductor devices with shield and gate contacts
Methods of manufacturing power semiconductor devices include forming an epitaxial and dielectric layer, patterning and etching the dielectric layer, forming a...
US-8,129,244 Method for fabricating semiconductor device
A method for fabricating a semiconductor device includes forming a plurality of first trenches by etching a substrate, forming a plurality of buried bit lines...
US-8,129,243 Methods of forming non-volatile memory having tunnel insulator of increasing conduction band offset
Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers...
US-8,129,242 Method of manufacturing a memory device
A method of manufacturing a flash memory device having an enhanced gate coupling ratio includes steps of forming a first semiconductor layer on a substrate and...
US-8,129,241 Method for forming a shielded gate trench FET
A method for forming a shielded gate field effect transistor (FET) includes forming a plurality of trenches in a semiconductor region and forming a shield...
US-8,129,240 Methods of forming a plurality of capacitors
A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area...
US-8,129,239 Semiconductor device having an expanded storage node contact and method for fabricating the same
A semiconductor device is disclosed that stably ensures an area of a storage node contact connected to a junction region in an active region of the...
US-8,129,238 Semiconductor devices having dual trench, methods of fabricating the same, and electronic system having the same
A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system...
US-8,129,237 Vertical light-emitting diode device structure with Si.sub.xN.sub.y layer
A vertical light-emitting diode (VLED) structure fabricated with a Si.sub.xN.sub.y layer responsible for providing increased light extraction out of a roughened...
US-8,129,236 Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate...
After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch...
US-8,129,235 Method of fabricating two-step self-aligned contact
A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region therein. Next, a lower...
US-8,129,234 Method of forming bipolar transistor integrated with metal gate CMOS devices
A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while...
US-8,129,233 Method for fabricating thin film transistor
A method for fabricating a thin film transistor (TFT) on a substrate includes forming a gate electrode; forming a semiconductor layer being insulated from the...
US-8,129,232 Semiconductor device and method of manufacturing the same
A semiconductor device having a CMOS structure, wherein, in manufacturing a CMOS circuit, an impurity element which imparts p-type conductivity to the active...
US-8,129,231 Method of manufacture for semiconductor package with flow controller
A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered...
US-8,129,230 Underfill method and chip package
A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the...
US-8,129,229 Method of manufacturing semiconductor package containing flip-chip arrangement
A metal leadframe to be used in manufacturing a "flip-chip" type semiconductor package is treated to form a metal plated layer in an area to be contacted by a...
US-8,129,228 Manufacturing method for integrating a shunt resistor into a semiconductor package
An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to...
US-8,129,227 Semiconductor device having grooved leads to confine solder wicking
A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes...
US-8,129,226 Power lead-on-chip ball grid array package
A packaging assembly (30), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die (52) by...
US-8,129,225 Method of manufacturing an integrated circuit module
A method includes providing an integral array of first carriers, arranging first semiconductor chips on the first carriers, and arranging an integral array of...
US-8,129,224 Stud bumps as local heat sinks during transient power operations
A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding...
US-8,129,223 Nanotube modified solder thermal intermediate structure, systems, and methods
An apparatus and system, as well as fabrication methods therefor, may include a thermal intermediate structure with metal decorated carbon nanotubes...
US-8,129,222 High density chip scale leadframe package and method of manufacturing the package
An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face...
US-8,129,221 Semiconductor package and method of forming the same
Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a...
US-8,129,220 Method and system for bonding electrical devices using an electrically conductive adhesive
A system for bonding electrical devices using an electrically conductive adhesive to adhere the electrical devices together, the system comprising: an...
US-8,129,219 Semiconductor module, method for manufacturing the semiconductor module and portable device carrying the same
In a semiconductor module where a metal sheet, an insulating layer and a circuit element are stacked in a manner that the insulating layer is penetrated with a...
US-8,129,218 Self-aligned, planar phase change memory elements and devices, systems employing the same and method of forming...
Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second...
US-8,129,217 Method for producing at least one multilayer body, and multilayer body
The invention concerns a process for the production of a multi-layer body, wherein the multi-layer body includes at least two functional layers on a top side of...
US-8,129,216 Method of manufacturing solar cell with doping patterns and contacts
A method of manufacturing a solar cell. The method includes the steps of providing a substrate, applying a first dopant to a first surface, applying a second...
US-8,129,215 Method for producing high temperature thin film silicon layer on glass
A method for producing a High Temperature Thin Film Layer On Glass (HTTFLOG) of silicon, which is a precursor component of thin film transistors (TFTs). The...
US-8,129,214 Phase change memory devices having dual lower electrodes and methods of fabricating the same
A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the...
US-8,129,213 Solid-state imaging device and method for manufacturing the same
Disclosed herein is a solid-state imaging device including: a semiconductor layer; a charge accumulation region configured to be formed inside the semiconductor...
US-8,129,212 Surface cleaning and texturing process for crystalline solar cells
Methods for surface texturing a crystalline silicon substrate are provided. In one embodiment, the method includes providing a crystalline silicon substrate,...
US-8,129,211 Dye-sensitized solar cell comprising metal oxide nanoball layer and preparation method thereof
A dye-sensitized solar cell comprising a semiconductor electrode prepared by spraying a metal oxide nanoparticle dispersion on a conductive substrate using an...
US-8,129,210 Manufacturing method of microstructure
A manufacturing method of a microstructure which enables production of a deep and narrow microstructure in a GaN semiconductor with high precision is provided....
US-8,129,209 Method for fabricating a semiconductor component based on GaN
A semiconductor component has a plurality of GaN-based layers, which are preferably used to generate radiation, produced in a fabrication process. In the...
US-8,129,208 n-Type conductive aluminum nitride semiconductor crystal and manufacturing method thereof
This invention provides a self supporting substrate which consists of a n-type conductive aluminum nitride semiconductor crystal and is useful for manufacturing...
US-8,129,207 Light emitting diode having a thermal conductive substrate and method of fabricating the same
Disclosed are a light emitting diode having a thermal conductive substrate and a method of fabricating the same. The light emitting diode includes a thermal...
US-8,129,206 Light emitting diode package and method of making the same
The light emitting diode package of the present invention uses photosensitive materials to form phosphor encapsulations or a phosphor layer, which can be...
US-8,129,205 Solid state lighting devices and associated methods of manufacturing
Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light...
US-8,129,204 Liquid discharge head substrate, liquid discharge head using the substrate, and manufacturing method therefor
Provided is a liquid discharge head substrate including: a substrate; a heating resistor layer formed on the substrate; a flow path for a liquid; a wiring layer...
US-8,129,203 Auto feedback apparatus for laser marking
A method of manufacturing integrated circuits includes measuring a reflectivity value of a wafer. An optimum energy level for laser marking the wafer is...
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