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Patent # Description
US-8,139,457 Systems and methods for low latency media defect detection
Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed...
US-8,139,456 Optical recording method and optical recording device
In a recording method for recording information on an optical recording medium (500) according to the parameters of a write strategy by repeatedly recording...
US-8,139,455 Information storage medium and method and apparatus for recording/reproducing data on/from the same
An apparatus for recording data on an information storage medium including a plurality of recording layers, each having a user data area, on which data is...
US-8,139,454 Recording and reproducing apparatus and method
A Spare Area kept unused on a disk is available for use other than spare processing, or Defect Management process, and compatibility of the disk is at least...
US-8,139,453 Buffering control method, and buffering control device
When receiving the reproduced data from the optical disc and buffering same, the buffering from the correct position can be started on the basis of the...
US-8,139,452 Record carrier comprising an additional sync-color pattern and method and device for use with such record carrier
The invention relates to a format for storing information on an optical recording medium. According to said format the record carrier comprises a ...
US-8,139,451 Information recording apparatus and information recording method
An information recording apparatus for recording additional content on a medium on which a title including one or more files is already recorded, includes means...
US-8,139,450 Amplifier circuit and optical pickup device
An amplifier circuit and an optical pickup device supporting multi-layered optical discs and hi-speed play mode. The amplifier circuit includes photodiodes 11...
US-8,139,449 Method and apparatus for eliminating errors in a seek operation on a recording medium
A method and apparatus for eliminating errors in a seek operation on a recording medium are provided. Given a target address on a recording medium, a reading...
US-8,139,448 Slider with integrated thermally-assisted recording (TAR) head and vertical-cavity surface-emitting laser...
A thermally-assisted recording (TAR) slider has an integrated TAR head and an integrated external-cavity VCSEL. The TAR head is integrated with the slider at...
US-8,139,447 Heat-assisted magnetic recording head with near-field light generating element
A heat-assisted magnetic recording head includes a magnetic pole, a waveguide, a near-field light generating element, and a substrate on which they are stacked....
US-8,139,446 Audio system
An audio system includes a key input section and a microcomputer, and enables playback volume level control that will meet the demand of a user. The key input...
US-8,139,445 Stepping motor control circuit and analog electronic watch
A stepping motor control circuit includes a rotation detecting means which detects an induced signal generated by rotation of a rotor of a stepping motor, and...
US-8,139,444 Routine clock with variable indicators
A routine clock for visually and audibly identifying time periods and events is disclosed. The routine clock may have indicators placed on the routine clock...
US-8,139,443 Underwater sound projector system and method of producing same
An underwater sound projector system comprises multiple sound projectors, each sound projector being capable of producing acoustic pressures. The sound...
US-8,139,442 Robust underwater communication system
A robust underwater communication system, for communication between an acoustic signal transmitter and a remotely positioned acoustic signal receiver, wherein...
US-8,139,441 Method for bispectral picking of anelliptical NMO correction parameters
Method of determining the velocity V and anellipticity .eta. parameters for processing seismic traces in a common midpoint (CMP) gather comprising:--a...
US-8,139,440 Spectral conditioning for surface seismic data
A method for spectrally conditioning surface seismic data. In one implementation, the method may include correcting surface seismic data for distortions due to...
US-8,139,439 Methods and systems for seismic sensor calibration
Methods and systems for calibrating seismic sensors configured or designed for use in seismic signal detection. According to certain embodiments of the present...
US-8,139,438 Semiconductor storage device and memory system
A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that...
US-8,139,437 Wordline driving circuit of semiconductor memory device
Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an...
US-8,139,436 Integrated circuits, systems, and methods for reducing leakage currents in a retention mode
An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with...
US-8,139,435 Data storage apparatus and control method of data storage apparatus
In a data storage apparatus having data storage means, if it is judged that a condition of transitioning the data storage apparatus into a power saving state is...
US-8,139,434 Methods and apparatus for voltage sensing and reporting
Semiconductor devices comprising at least one voltage sensor for sensing an operating voltage associated with an operational circuit of the semiconductor...
US-8,139,433 Memory device control for self-refresh mode
To ensure that a memory device operates in self-refresh mode, the memory controller includes (1) a normal-mode output buffer for driving a clock enable signal...
US-8,139,432 Variable resistance memory device and system thereof
A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells,...
US-8,139,431 Structure and methods for measuring margins in an SRAM bit
Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array...
US-8,139,430 Power-on initialization and test for a cascade interconnect memory system
A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus...
US-8,139,429 Output enable signal generating circuit and method of semiconductor memory apparatus
An output enable signal generating circuit for a semiconductor memory apparatus includes an output control unit configured to receive CAS latency information...
US-8,139,428 Method for reading and writing a block interleaver and the reading circuit thereof
A method for writing a memory of a block interleaver determines in a bit-wise manner whether to write data into the memory. A method for reading a memory of a...
US-8,139,427 Nonvolatile memory device
A nonvolatile memory device includes a data sense amplifier configured to supply a data detection current to a memory cell and detect a data detection voltage...
US-8,139,426 Dual power scheme in memory circuit
A semiconductor memory device includes address signal level shifters configured to transform a low level address signal into a higher level address signal. A...
US-8,139,425 Voltage regulation method and memory applying thereof
A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory includes the following...
US-8,139,424 Semiconductor apparatus
A semiconductor apparatus includes a first internal voltage generator generating a first internal voltage in response to an external power supply voltage, a...
US-8,139,423 Write driving device
A write driving device includes a buffer unit, a duration signal generation unit, and a data input clock pulse generation unit. The buffer unit is configured to...
US-8,139,422 Buffer circuit of semiconductor memory apparatus
A buffer circuit of a semiconductor memory apparatus includes a compensation voltage generation unit configured to generate a compensation voltage in response...
US-8,139,421 Erase degradation reduction in non-volatile memory
Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate...
US-8,139,420 Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device capable of reading and verifying a negative threshold cell by biasing a source line and a well line to a positive...
US-8,139,419 Programming methods and memories
Methods of programming memory cells, and memories incorporating such methods, are disclosed. In at least one embodiment, programming is accomplished by applying...
US-8,139,418 Techniques for controlling a direct injection semiconductor memory device
Techniques for controlling a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized...
US-8,139,417 Flash memory device and read method
A flash memory device includes a word line decoder configured to receive a row address, and decode a selected word line and a neighboring non-selected word line...
US-8,139,416 Operation methods for memory cell and array for reducing punch through leakage
A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate...
US-8,139,415 Phase-change memory device
A phase-change memory device is capable of reducing current consumption and preventing performance deterioration caused due to line load by improving a process...
US-8,139,414 Source side asymmetrical precharge programming scheme
A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically...
US-8,139,413 Flash memory device
A flash memory device can include a memory cell array that includes a plurality of memory blocks, where each of the memory blocks has memory cells arranged at...
US-8,139,412 Systematic error correction for multi-level flash memory
In accordance with exemplary embodiments, a multi-level flash memory employs error correction of systematic errors when reading multi-level flash memory. Error...
US-8,139,411 pFET nonvolatile memory
A non-volatile memory integrated circuit includes multiple memory cells, each memory cell including a first MOS transistor, a first control capacitor, and a...
US-8,139,410 Trap-charge non-volatile switch connector for programmable logic
A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap...
US-8,139,409 Access signal adjustment circuits and methods for memory cells in a cross-point array
Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to...
US-8,139,408 Scalable electrically eraseable and programmable memory
A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing...
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