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Patent # Description
US-8,138,603 Redundancy design with electro-migration immunity
An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a...
US-8,138,602 Solder interconnect pads with current spreading layers
Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a...
US-8,138,601 Ultrasonic measuring method, electronic component manufacturing method, and semiconductor package
The waveform signals of ultrasonic waves reflected by a plurality of interfaces in a measurement object are received, the waveform signal of a reflected wave on...
US-8,138,600 Semiconductor device and method of manufacturing the same
A semiconductor device is provided, which is capable of improving mounting flexibility relatively and increasing general versatility, as well as realizing heat...
US-8,138,599 Wireless communication device integrated into a single package
A method, apparatus and system with an autonomic, self-healing polymer capable of slowing crack propagation within the polymer and slowing delamination at a...
US-8,138,598 Semiconductor device and a manufacturing method of the same
In a non-insulated DC-DC converter having a circuit in which a power MOS.cndot.FET high-side switch and a power MOS.cndot.FET low-side switch are connected in...
US-8,138,597 Semiconductor assembly that includes a power semiconductor die located in a cell defined by a patterned polymer...
A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to...
US-8,138,596 Method for manufacturing an element having electrically conductive members for application in a microelectronic...
A microelectronic package (31) has a microelectronic device, which is encapsulated in a quantity of material (27), and a lead frame element (15) for enabling...
US-8,138,595 Integrated circuit packaging system with an intermediate pad and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: forming an elevated contact above and between a lead and a die pad that is coplanar...
US-8,138,594 Semiconductor device and manufacturing method of a semiconductor device
A semiconductor device of the present invention comprises a substrate and a first semiconductor element. The substrate comprises an inner layer conductor and a...
US-8,138,593 Packaged microchip with spacer for mitigating electrical leakage between components
A packaged microchip has a base, at least one spacer coupled to the base, and first and second microchips mounted to the at least one spacer. The at least one...
US-8,138,592 Planar array contact memory cards
A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of...
US-8,138,591 Integrated circuit package system with stacked die
An integrated circuit package system comprising forming a trace frame including: fabricating a sacrificial substrate; forming a first series of bonding pads...
US-8,138,590 Integrated circuit package system with wire-in-film encapsulation
An integrated circuit package system includes: connecting a carrier and an integrated circuit mounted thereover; preforming a wire-in-film encapsulation having...
US-8,138,589 Semiconductor device and method of fabricating the same
In fabrication of a semiconductor device mounted on a wiring board, a semiconductor circuit portion is formed over a glass substrate. Then, an interposer having...
US-8,138,588 Package stiffener and a packaged device using the same
A package frame for use in packaging microelectromechanical devices and/or spatial light modulators comprises a frame, a stiffener, and a heat dissipater.
US-8,138,587 Device including two mounting surfaces
A device including two mounting surfaces. One embodiment provides a power semiconductor chip and having a first electrode on a first surface and a second...
US-8,138,586 Integrated circuit package system with multi-planar paddle
An integrated circuit package system includes a multi-planar paddle having an uplift rim and an attached integrated circuit over the uplift rim of the...
US-8,138,585 Four mosfet full bridge module
A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two...
US-8,138,584 Method of forming a semiconductor package and structure thereof
An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed by forming a conductive layer (34, 46) over an encapsulant (32). The...
US-8,138,583 Diode having reduced on-resistance and associated method of manufacture
A diode structure having a reduced on-resistance in the forward-biased condition includes semiconductor layers, preferably of silicon carbide. The anode and...
US-8,138,582 Impurity introducing apparatus having feedback mechanism using optical characteristics of impurity introducing...
An impurity doping system is disclosed, which includes an impurity doping device for doping an impurity into a surface of a solid state base body, a measuring...
US-8,138,581 Semiconductor device with channel stop trench and method
A semiconductor device is provided which includes a semiconductor substrate having a first surface, an active area and a peripheral area. The semiconductor...
US-8,138,580 Adhesive composition for electronic components, and adhesive sheet for electronic components using the same
In order to provide an adhesive composition for electronic components that is excellent in adhesion durability under long-term high temperature conditions,...
US-8,138,579 Structures and methods of forming SiGe and SiGeC buried layer for SOI/SiGe technology
Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried...
US-8,138,578 Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device
A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer...
US-8,138,577 Pulse-laser bonding method for through-silicon-via based stacking of electronic components
There is described a method of forming a through-silicon-via to form an interconnect between two stacked semiconductor components using pulsed laser energy. A...
US-8,138,576 Production method and production apparatus of tin or solder alloy for electronic components, and solder alloy
The invention provides a technique and a device that dramatically improve joint reliability of miniature joints of fine electronic components. According to the...
US-8,138,575 Integrated circuit including a reverse current complex
An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers,...
US-8,138,574 PCM with poly-emitter BJT access devices
A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access...
US-8,138,573 On-chip heater and methods for fabrication thereof and use thereof
An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located...
US-8,138,572 Semiconductor device and method for fabricating the same
The present invention relates to a semiconductor and manufacturing method thereof, in which a nano tube structure is vertically grown to form a lower electrode...
US-8,138,571 Semiconductor device comprising isolation trenches inducing different types of strain
By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active...
US-8,138,570 Isolated junction field-effect transistor
An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall...
US-8,138,569 Guard ring structures and method of fabricating thereof
A guard ring structure for use in a semiconductor device. The guard ring structure includes a semiconductor layer stack having a first layer and a second layer...
US-8,138,568 Transparent carbon nanotube electrode using conductive dispersant and production method thereof
Disclosed is a transparent carbon nanotube (CNT) electrode using a conductive dispersant.degree. The transparent CNT electrode comprises a transparent substrate...
US-8,138,567 Materials, fabrication equipment, and methods for stable, sensitive photodetectors and image sensors made therefrom
Optically sensitive devices include a device comprising a first contact and a second contact, each having a work function, and an optically sensitive material...
US-8,138,566 Integrated circuit chip made secure against the action of electromagnetic radiation
A chip for a chip-incorporating portable article having a card format, such as for smartcards. The chip includes a silicon substrate layer having integrated...
US-8,138,565 Lateral double diffused metal oxide semiconductor device and method of making the same
An LDMOS device and method for making the same are disclosed. The LDMOS device comprises a first well, a second well, a third well, a first ion implantation...
US-8,138,564 Image sensor unit and image sensor apparatus
An image sensor unit includes a fixed substrate, a movable substrate, an actuate section including an actuator for moving the movable substrate against the...
US-8,138,563 Circuit structures and methods with BEOL layers configured to block electromagnetic edge interference
Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge...
US-8,138,562 Bit line preparation method in MRAM fabrication
A MRAM structure is disclosed that includes a metal contact bridge (MCB) which provides an electrical connection between a MTJ top electrode and an overlying...
US-8,138,561 Structure and method to fabricate high performance MTJ devices for spin-transfer torque (STT)-RAM
A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by a NOX process, a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel layer...
US-8,138,560 Microstructure, micromachine, and manufacturing method of microstructure and micromachine
Without sacrificial layer etching, a microstructure and a micromachine are manufactured. A separation layer 102 is formed over a substrate 101, and a layer 103...
US-8,138,559 Recessed drift region for HVMOS breakdown improvement
A high-voltage metal-oxide-semiconductor (HVMOS) device having increased breakdown voltage and methods for forming the same are provided. The HVMOS device...
US-8,138,558 Semiconductor device and method of forming low voltage MOSFET for portable electronic devices and data...
A semiconductor device has a well region formed within a substrate. A gate structure is formed over a surface of the substrate. A source region is formed within...
US-8,138,557 Layout structure of MOSFET and layout method thereof
A layout structure of a MOSFET is provided. The layout structure of the MOSFET includes a plurality of MOSFET cells, a first source/drain metal bus structure...
US-8,138,556 Pre-released structure device
A pre-released structure device comprising: at least one first stacking, comprising at least one first layer based on at least one first material, arranged...
US-8,138,555 Semiconductor device and its manufacturing method
An object of the present invention is to provide an active matrix type display unit having a pixel structure in which a pixel electrode formed in a pixel...
US-8,138,554 Semiconductor device with local interconnects
A semiconductor device with local interconnects is provided. The semiconductor device comprises a first gate line structure and a second gate line structure...
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