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Patent # Description
US-8,140,917 Stream recovery method, stream recovery program and failure recovery apparatus
Stream data is structured including data tuples as a query process target and a recovery point tuple for indicating a position of the data tuples in the stream...
US-8,140,916 Unit for predicting malfunction of an apparatus
According to one embodiment, a malfunction predicting unit includes a level reduction unit, a first buffer gate unit, a second buffer gate unit, a comparator...
US-8,140,915 Detecting apparatus, system, program, and detecting method
A detecting apparatus including a cluster storing unit that stores, for each of clusters into which execution time of previously executed monitored tasks are...
US-8,140,914 Failure-model-driven repair and backup
A predictive failure model is used to generate a failure prediction associated with a node. A repair or backup action may also be determined to perform on the...
US-8,140,913 Apparatus and method for monitoring computer system, taking dependencies into consideration
A system monitoring apparatus specifies an intentionally shutdown system component or monitoring target, and a different monitoring target that is dependent...
US-8,140,912 Semiconductor integrated circuits and method of detecting faults of processors
A semiconductor integrated circuit comprising a processor having an output signal of instruction log information and being operable in a program in memory is...
US-8,140,911 Dynamic software tracing
A method, computer program product and system for dynamically changing a trace level, and optionally the trace size, depending on a recognized critical path. In...
US-8,140,910 Mismatched operation and control correction
A system and method for a software override capability for enforcing a predetermined state for an otherwise hardware-programmable device. Software that may...
US-8,140,909 Efficient method to detect disk write errors
A write error detection mechanism for a computer data disk drive or storage controller writes and then verifies data to detect disk write errors. It allows the...
US-8,140,908 System and method of client side analysis for identifying failing RAM after a user mode or kernel mode exception
A process executing on a computing system may encounter an exception. Pointers or other references created by the exception may identify portions of the...
US-8,140,907 Accelerated virtual environments deployment troubleshooting based on two level file system signature
Troubleshooting virtual environment deployment based on two level file system signatures, in one aspect, may include creating a first level file system...
US-8,140,906 Techniques for recovering data from cold images
Techniques for recovering data from cold images are disclosed. In one particular exemplary embodiment, the techniques may be realized as a computer implemented...
US-8,140,905 Incremental problem determination and resolution in cloud environments
Installation files are annotated, which annotations may trigger system snapshots to be taken at a plurality of points during the execution of the installation...
US-8,140,904 Application portal testing
A first test script that includes at least one first step for executing a test of a test portal is provided in a computing device. An indication that an event...
US-8,140,903 Hardware process trace facility
A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread...
US-8,140,902 Internally controlling and enhancing advanced test and characterization in a multiple core microprocessor
A mechanism is provided for internally controlling and enhancing advanced test and characterization in a multiple core microprocessor. To decrease the time...
US-8,140,901 Validation of processors using a self-generating test case framework
A method for testing processors is disclosed. The method includes generating a plurality of pools, where each pool includes a test program that includes a...
US-8,140,900 Establishing a connection between a testing and/or debugging interface and a connector
This invention relates to automatically establishing a connection between a testing and/or debugging interface to an integrated circuit and a connector of an...
US-8,140,899 Method and system for diagnosing a computer system
A method includes determining a rule lookup key for a computer system to be diagnosed, retrieving a diagnostic rule set associated with the rule lookup key, and...
US-8,140,898 Techniques for gathering evidence for performing diagnostics
Techniques for performing diagnostics for a monitored system. In one embodiment, an aggregate model built using a set of models is used to determine a set of...
US-8,140,897 Testing method for complex systems
A method of testing a complex system of components is provided. The method includes providing a test log for each component, each test log comprising a list of...
US-8,140,896 System and method for downloading system program
A system and method thereof are provided. The example method may include downloading first information, from a host device, associated with an operation of a...
US-8,140,895 Method and system for recovering SIP transaction
A method and system for recovering a SIP transaction. The method including monitoring an event related to transaction change; recording information related to...
US-8,140,894 Transaction regions in graphical computer-implemented methods of processing data
A method including: displaying operation icons representing operations to be performed, a user selecting and arranging the operation icons to define a flow of...
US-8,140,893 Fault-tolerant system
In a lockstep fault-tolerant system (10), each subsystem (1, 2) includes bridges (71 to 75) positioned between a CPU (21) and memory (11), between a CPU (22)...
US-8,140,892 Configuration of memory management techniques selectively using mitigations to reduce errors
Techniques for performing memory management to mitigate memory errors. In accordance with the principles described herein, a memory management module may be...
US-8,140,891 Method of determining defects in information storage medium, recording/reproducing apparatus using the same,...
A method of determining whether a defect exists on an information storage medium is provided along with a recording/reproducing apparatus using the same. Such a...
US-8,140,890 Relocating bad block relocation (BBR) directory upon encountering physical media defect on a disk
Apparatus, method and program product for relocating Bad Block Relocation Directory (BBRD) on a disk storage pre-allocate a number of areas for BBRD in...
US-8,140,889 Dynamically reassigning a connected node to a block of compute nodes for re-launching a failed job
Methods, systems, and products for dynamically reassigning a connected node to a block of compute nodes for re-launching a failed job that include: identifying...
US-8,140,888 High availability network processing system
A host receives messages from a network processing device. Messages received from a primary port are processed and also forwarded to a standby host over a...
US-8,140,887 System and method for providing data services via a network
A method and system are provided for performing an activity. Accordingly, an activity to be performed is determined, a stored hierarchy is examined indicating a...
US-8,140,886 Apparatus, system, and method for virtual storage access method volume data set recovery
An apparatus, system, and method are disclosed for Virtual Storage Access (VSAM) Volume Data Set (VVDS) recovery. A store module stores a data set name and data...
US-8,140,885 Accounting for microprocessor resource consumption
Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor...
US-8,140,884 Efficient time-based memory counters
Some embodiments of efficient time-based memory counters have been presented. In one embodiment, a set of arrays of counters is arranged in layers to associate...
US-8,140,883 Scheduling of pipelined loop operations
Pipelined loop operations are efficiently scheduled. A preliminary as soon as possible (ASAP) schedule for a data operation in a pipelined loop is determined. A...
US-8,140,882 Serial bus clock frequency calibration system and method thereof
A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second...
US-8,140,881 Circuitry and method for detection of network node aging in communication networks
The network node includes a local crystal oscillator for providing a time reference derived from the clock signal produced by the local crystal oscillator, a...
US-8,140,880 Data control unit
A data control unit includes a primary power supply line to which a primary power supply voltage is supplied; a secondary power source line to which a secondary...
US-8,140,879 System and method for information handling system power management by variable direct current input
A power manager of an information handling system selectively commands a first or second source voltage from an AC-to-DC adapter based upon power consumption of...
US-8,140,878 Power conservation technique for blade computer systems
A blade computer system includes a plurality of client devices, a blade enclosure having a plurality of blades therein, and an allocation server configured to...
US-8,140,877 Reducing power consumption in a system operating in a power saving mode
An apparatus is provided, for reducing power consumption in a system operating in a power saving mode, comprising a controller, an oscillator circuit and a...
US-8,140,876 Reducing power consumption of components based on criticality of running tasks independent of scheduling...
A method, apparatus, and program product are provided for managing power consumption in a computer system based on the degree with which performance of tasks...
US-8,140,875 Integrated circuit apparatus
An integrated circuit apparatus may include: a plurality of power domains to which power voltage is separately supplied; a plurality of circuit macros belonging...
US-8,140,874 Integrated device, layout method thereof, and program
An integrated device includes at least one data processing device and at least one memory macro accessible by the data processing device. The data processing...
US-8,140,873 User imposed power constraints on web server based on user preferences
Web application users are able to specify power constraints for remote web servers. These may be based on individual performance needs and energy-conservation...
US-8,140,872 Restoring processor context in response to processor power-up
A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the...
US-8,140,871 Wake on Lan for blade server
A computer implemented method, a tangible computer medium, and a data processing system are provided for waking a blade server from an operational state of...
US-8,140,870 PWM timer for power supply
A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary...
US-8,140,869 Central power management
The present invention provides a central power management method and system, a device side agent and a central power management controller. The central power...
US-8,140,868 Performance conserving power consumption reduction in a server system
A method for managing power in a data processing system having multiple components includes determining a power budget for the system. Activity levels during a...
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