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Patent # Description
US-8,146,068 Managing heuristic properties
A computer implemented method, system and computer program product for managing heuristic properties for controlling an optimization transformation in a...
US-8,146,067 Efficient data reorganization to satisfy data alignment constraints
Vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores is presented. In the framework presented...
US-8,146,066 Systems and methods for caching compute kernels for an application running on a parallel-processing computer system
A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime...
US-8,146,065 Running time of short running applications by effectively interleaving compilation with computation in a...
A computer implemented method, apparatus, and computer program product for managing just-in-time compilation. The process designates a set of compilation...
US-8,146,064 Dynamically controlling a prefetching range of a software controlled cache
Dynamically controlling a prefetching range of a software controlled cache is provided. A compiler analyzes source code to identify at least one of a plurality...
US-8,146,063 Translation of a series of computer instructions
A series (20) of original instructions for a single processor is translated into implementing instructions for executions distributed over a plurality of...
US-8,146,062 Method and process to automatically perform test builds of translated files for a software product
A method, apparatus, and computer program instructions for automatically performing test builds of natural language translated files for a software product....
US-8,146,061 Systems and methods for graphics hardware design debugging and verification
Disclosed are systems and methods for debugging and analyzing graphics hardware designs. Hardware designs are represented by a software model implemented in a...
US-8,146,060 Data processing system and method for execution of a test routine in connection with an operating system
In a system or a method for execution of a test routine in connection with a test operating system, the program data for provision of an administration...
US-8,146,059 Feeding test metrics into an integrated development environment to aid software developers to improve code quality
An IDE or program operable with an IDE retrieves automated test results for a code sequence. The IDE or separate program detects the code sequence during source...
US-8,146,058 Measuring quality of software modularization
Quality of modularization of source code is tested using different perspectives such as a structural modularity perspective, an architectural modularity...
US-8,146,057 Instrumentation system and method for testing software
One or more test controls within code under test are enabled and then executing the code under test is executed. When enabled, the test control will interact...
US-8,146,056 Debugging a computer program by interrupting program execution in response to access of unused I/O port
A method, computer-readable medium, and apparatus for debugging a computer program utilizing breakpoints triggered by accessing a rarely used or unused I/O port...
US-8,146,055 Generating sequence diagrams using call trees
A software tool is provided to analyze static source code. Source Code files are selected to define the project work space. A class and a method in the class...
US-8,146,054 Hybrid data object model
Computer implemented method, system and computer usable program code for processing a data object, for example, for searching for, creating or updating a data...
US-8,146,053 Graphical programming environment with first model of computation that includes a structure supporting second...
System and method for creating a graphical program that uses multiple models of computation (MoC). A first plurality of graphical program elements is assembled...
US-8,146,052 Method and system for hierarchical hardware mapping for software design
The present disclosure is directed toward a method for hierarchical hardware mapping in a software design environment. The method comprises the step of...
US-8,146,051 Method and computer program product for providing a representation of software modeled by a model
A computer program product and a method for providing a graphical representation of a software, the method includes: receiving semantic concern defining...
US-8,146,050 Graphical program with physical simulation and data flow portions
Various embodiments of systems and methods are described in which system simulation techniques are combined with graphical programming techniques in a common...
US-8,146,049 Support apparatus and design support method
According to one embodiment, a design support apparatus determines one of a first impedance between a power plane and a ground plane in the printed circuit...
US-8,146,048 System and method for removing T-point elements with unused stubs from a PCB layout design
A system and method for removing T-point elements with unused stubs from a printed circuit board (PCB) layout design obtains each signal line including one or...
US-8,146,047 Automation method and system for assessing timing based on gaussian slack
An automated design process using a computer system includes identifying a set of timing endpoints in a circuit defined by a machine-readable file. Values of...
US-8,146,046 Structures for semiconductor structures with error detection and correction
A design structure including design data describing a semiconductor structure. The semiconductor structure includes a first semiconductor chip and a second...
US-8,146,045 High-level circuit architecture optimizer
A method for optimizing a high-level circuit architecture for an integrated circuit is described. Descriptions of components of the circuit architecture and...
US-8,146,044 Method of designing a semiconductor device
Aiming at providing a method of designing a semiconductor device capable of producing a semiconductor device which expresses performances adapted to required...
US-8,146,043 Huygens' box methodology for signal integrity analysis
A method for performing a signal integrity analysis on an integrated circuit (IC) that includes a plurality of scatterers by dividing the scatterers into...
US-8,146,042 Method and system for optimized circuit autorouting
An approach is provided for selectively optimizing a circuit design to be physical implemented. The approach includes generating a circuit routing solution in...
US-8,146,041 Latch based optimization during implementation of circuit designs for programmable logic devices
A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the...
US-8,146,040 Method of evaluating an architecture for an integrated circuit device
A method of evaluating an architecture for an integrated circuit device is disclosed. The method comprises generating a library of primitives for a...
US-8,146,039 Optimal distance based buffer tree for data path and clock
A device development tool selects a source component and identifies a plurality of sink components in a device design layout. The device development tool...
US-8,146,038 Method for conjecturing effective width and effective length of gate
A method for conjecturing the effective size, i.e. the effective width or effective length, of a gate is disclosed. First, a first design gate group including a...
US-8,146,037 Method for generating a deep N-well pattern for an integrated circuit design
A method for the design and layout for a patterned deep N-well. A tile is specified as a fundamental building block for the deep N-well pattern. The tile...
US-8,146,036 Circuit for and method of determining a process corner for a CMOS device
A circuit for determining a process corner for a CMOS device of an integrated circuit is disclosed. The circuit comprises a CMOS monitoring circuit comprising...
US-8,146,035 Power estimation of a circuit design
Approaches for estimating power consumption of a circuit from a circuit design. According to one embodiment, a representation of the circuit design specifies a...
US-8,146,034 Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs...
A mechanism is provided for efficient redundancy identification, redundancy removal, and sequential equivalence checking with designs including memory arrays....
US-8,146,033 Monitor position determining apparatus and monitor position determining method
A monitor position determining apparatus includes an acquiring unit that acquires design data concerning circuit elements arranged in a layout of a...
US-8,146,032 Method and apparatus for performing RLC modeling and extraction for three-dimensional integrated circuit...
One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During...
US-8,146,031 Method for generating and evaluating a table model for circuit simulation
A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table...
US-8,146,030 Interactive loop configuration in a behavioral synthesis tool
A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate...
US-8,146,029 Synthesis of electronic circuits
The invention relates to a method of synthesizing an electronic circuit for performing a function. The method comprises programming the function using a...
US-8,146,028 Duplicate design flow for mitigation of soft errors in IC operation
An integrated circuit ("IC") (100) is configured to have two instantiations of a user design (103, 105). Register values from the first instantiation (RA1, RA2,...
US-8,146,027 Creating interfaces for importation of modules into a circuit design
A computer-implemented method of incorporating a module within a circuit design can include, responsive to identifying the module to be imported into the...
US-8,146,026 Simultaneous photolithographic mask and target optimization
A mechanism is provided for simultaneous photolithographic mask and target optimization (SMATO). A lithographic simulator generates an image of a mask shape on...
US-8,146,025 Method for correcting layout pattern using rule checking rectangle
A method for correcting layout pattern is disclosed. The method includes the steps of: providing a layout pattern having at least one segment; forming a...
US-8,146,024 Method and system for process optimization
A method and apparatus for process optimization is provided. Process optimization improves parametric and functional yield post mask manufacturing.
US-8,146,023 Integrated circuit fabrication process convergence
A method for selecting a process for a new integrated circuit design. Structures that are used in existing integrated circuit designs are identified, as well as...
US-8,146,022 Mask pattern data generation method, mask manufacturing method, semiconductor device manufacturing method, and...
According to an aspect of the present invention, there is provided a mask pattern data generation method including: a first step of obtaining a mask data...
US-8,146,021 User interface for path distortion and stroke width editing
A technique for modifying a stretch of path is disclosed. The technique includes receiving an indication of a drag gesture associated with a designated point on...
US-8,146,020 Enhanced detection of circular engagement gesture
The enhanced detection of a circular engagement gesture, in which a shape is defined within motion data, and the motion data is sampled at points that are...
US-8,146,019 Method and terminal for playing and displaying music
A method and a terminal for playing and displaying music are provided. The method includes selecting a desired track in a playback mode, playing the selected...
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