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| Patent # | Description |
|---|---|
| US-8,145,918 |
Monitoring system processes energy consumption A method and system for monitoring power consumption of software applications. In a preferred embodiment of the present invention, a new feature is inserted in... |
| US-8,145,917 |
Security bootstrapping for distributed architecture devices Securing the boot phase of a computing system implemented as a distributed architecture device can be performed by a system or method that uses hash functions... |
| US-8,145,916 |
Finger sensing apparatus using encrypted user template and associated
methods A finger sensing apparatus may include an integrated circuit (IC) substrate, an array of finger sensing elements on the IC substrate, and encryption circuitry... |
| US-8,145,915 |
System and method for platform-independent biometrically secure
information transfer and access control The inventive data processing system and method enable verifiable secure transfer of information between two or more parties, each having access to at least one... |
| US-8,145,914 |
Client-side CAPTCHA ceremony for user verification A facility for performing a local human verification ceremony to obtain user verification is provided. Upon determining that user verification is needed to... |
| US-8,145,913 |
System and method for password protection Disclose are system, method and computer program product for protecting passwords from interception. An example method comprise: intercepting a plurality of... |
| US-8,145,912 |
System and method for using a visual password scheme A system and method for inputting a password. The system and method operates to associate unique non-descriptive graphical features with unique text-based... |
| US-8,145,911 |
System and method for the electronic management and execution of
transaction documents One aspect of the invention is a method for generating a certified electronic document that includes receiving identification information associated with a... |
| US-8,145,910 |
System and method to enforce collaboration rules for timestamps of a
collaboration event A method to enforce collaboration rules, in one example embodiment, comprises receiving a request to report a collaboration event to a collaboration workflow,... |
| US-8,145,909 |
Digitally signing an electronic document using seed data In one example embodiment, a method is illustrated that includes parsing seed data from digital content, the seed data identifying a signing entity,... |
| US-8,145,908 |
Web content defacement protection system A method and mechanism for protecting a website against defacement are provided. A content owner may associate content with a digital signature. The digital... |
| US-8,145,907 |
Secure data transfer The invention concerns secure data transfer from a first radio communication device of a first party to a second radio communication device. A random first... |
| US-8,145,906 |
Binding update method in MIPv6 Provided is a binding update method in MIPv6 which includes: a first step of generating, with a mobile node, a HoTI (Home Test Init) message and transmitting... |
| US-8,145,905 |
Method and apparatus for efficient support for multiple authentications Disclosed is a method for multiple EAP-based authentications in a wireless communication system. In the method, a first master session key (MSK) is generated in... |
| US-8,145,904 |
System and method for network edge data protection Disclosed are systems and methods which examine information communication streams to identify and/or eliminate malicious code, while allowing the good code to... |
| US-8,145,903 |
Method and system for a kernel lock validator An embodiment relates generally to a method of preventing resource access conflicts in a software component. The method includes intercepting a lock operation... |
| US-8,145,902 |
Methods and apparatus for secure processor collaboration in a
multi-processor system In a multi-processor system including a plurality of processors capable of being operatively coupled to the main memory and each processor including an... |
| US-8,145,901 |
System and method for nodes communicating in a shared network segment The invention provides a method and system for a network which includes a plurality of nodes, preferably routers, a shared network segment for communication... |
| US-8,145,900 |
Crypto-pointers for secure data storage This disclosure relates to pairing of a different cryptographic key with each pointer in a data structure to form a crypto-pointer. The cryptographic key is... |
| US-8,145,899 |
Creation of user digital certificate for portable consumer payment device A method for creating a digital certificate for a user issued by a reliant party, where the reliant party relies on an established cryptographic infrastructure... |
| US-8,145,898 |
Encryption/decryption pay per use web service A method, system, and computer program product for providing security for files transferred across a network, such as the Internet is provided. In one... |
| US-8,145,897 |
Direct anonymous attestation scheme with outsourcing capability A Direct Anonymous Attestation (DAA) scheme using elliptic curve cryptography (ECC) and bilinear maps. A trusted platform module (TPM) may maintain privacy of a... |
| US-8,145,896 |
System and method for implementing an enhanced transport layer security
protocol A system and method for implementing an enhanced transport layer security (ETLS) protocol is provided. The system includes a primary server, an ETLS servlet and... |
| US-8,145,895 |
Information transmission apparatus and method, information reception
apparatus and method, and... Described herein is an information transmission apparatus for encrypting and transmitting first data and second data, the information transmission apparatus... |
| US-8,145,894 |
Reconfiguration of an accelerator module having a programmable logic
device Reconfiguration of an accelerator module having a programmable logic device is described, where the reconfiguration is performed during runtime without... |
| US-8,145,893 |
Hot-plugging a memory device An extensible firmware interface (EFI) framework is to enable hot-plugging and hot-removal of memory devices. The security phase of the EFI may enable a cache... |
| US-8,145,892 |
Providing an electronic device security and tracking system and method A system and method for providing an electronic device security and tracking system and method (ESTSM). A method includes but is not limited to accepting a... |
| US-8,145,891 |
Bios-selectable data wiping system A data storage device includes a computer-readable medium encoded with a computer program that, when executed communicates with a basic input/output system... |
| US-8,145,890 |
Pipelined microprocessor with fast conditional branch instructions based
on static microcode-implemented... A microprocessor includes a memory that stores instructions of a non-user program to implement a user program instruction of the user-visible instruction set of... |
| US-8,145,889 |
Data processing system with branch target addressing using upper and lower
bit permutation A data processor or a data processing system used in compatible modes among which the number of bits of an address specifying a logical address space varies at... |
| US-8,145,888 |
Data processing circuit with a plurality of instruction modes, method of
operating such a data circuit and... A data processing circuit has an execution circuit (18) with a plurality of functional units (20). An instruction decoder (17) is operable in a first and a... |
| US-8,145,887 |
Enhanced load lookahead prefetch in single threaded mode for a
simultaneous multithreaded microprocessor A method, system, and computer program product are provided for enhancing the execution of independent loads in a processing unit. A processing unit detects if... |
| US-8,145,886 |
Changing processor functions by changing function information An information processing equipment comprises: a processor configured to refer to a function information indicating an assigned function and to execute a... |
| US-8,145,885 |
Apparatus for randomizing instruction thread interleaving in a
multi-thread processor A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are... |
| US-8,145,884 |
Apparatus, method and instruction for initiation of concurrent instruction
streams in a multithreading... A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing... |
| US-8,145,883 |
Preloading instructions from an instruction set other than a currently
executing instruction set A preload instruction in a first instruction set is executed at a processor. The preload instruction causes the processor to preload one or more instructions... |
| US-8,145,882 |
Apparatus and method for processing template based user defined
instructions A system implemented in hardware includes a main processing core decoding instructions for out of order execution. The instructions include template based user... |
| US-8,145,881 |
Data processing device and method A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and... |
| US-8,145,880 |
Matrix processor data switch routing systems and methods According to some embodiments, an integrated circuit comprises a microprocessor matrix of mesh-interconnected matrix processors. Each processor comprises a data... |
| US-8,145,879 |
Computer memory architecture for hybrid serial and parallel computing
systems In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store... |
| US-8,145,878 |
Accessing control and status register (CSR) A system may comprise one or more source agents, target agents, and a plurality of directory agents, which may determine the target agent to which one or more... |
| US-8,145,877 |
Address generation for quadratic permutation polynomial interleaving For address generation, a block size and a skip value are obtained, and at least one address, at least one increment value, and a step value are initialized.... |
| US-8,145,876 |
Address translation with multiple translation look aside buffers A data processing device employs a first translation look-aside buffer (TLB) to translate virtual addresses to physical addresses. If a virtual address to be... |
| US-8,145,875 |
Address translation circuit for a CPU An address translation circuit includes an area address holding section, an invert flag holding section, a match detection section, and a bit conversion... |
| US-8,145,874 |
System and method of data forwarding within an execution unit In an embodiment, a method is disclosed that includes, comparing, during a write back stage at an execution unit, a write identifier associated with a result to... |
| US-8,145,873 |
Data management method for network storage system and the network storage
system built thereof A data management method for network storage system that said network storage system includes a storage network, a cluster of storage servers that provide data... |
| US-8,145,872 |
Autonomic self-tuning of database management system in dynamic logical
partitioning environment Database partition monitoring and dynamic logical partition reconfiguration in support of an autonomic self-tunable database management system are provided by... |
| US-8,145,871 |
Dynamic allocation of virtual real memory for applications based on
monitored usage Mechanisms for dynamic reallocation of memory to an application, the memory being from a pool of virtual real memory allocated to a virtual client that executes... |
| US-8,145,870 |
System, method and computer program product for application-level
cache-mapping awareness and reallocation The present invention provides an improved method, system, and computer program product that can optimize cache utilization. In one embodiment, a kernel service... |
| US-8,145,869 |
Data access and multi-chip controller A single data bus to a memory device can be split up into a number of data bus portions, each of which is managed by a different respective controller chip of... |
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