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Patent # Description
US-8,143,154 Relaxed InGaN/AlGaN templates
A relaxed InGaN template is formed by growing a GaN or InGaN nucleation layer at low temperatures on a conventional base layer (e.g., sapphire). The nucleation...
US-8,143,153 Method for manufacturing semiconductor device
A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered...
US-8,143,152 Manufacturing method of semiconductor device having self-aligned contact connected to silicide layer on...
A semiconductor device 100 includes: a silicon substrate 102; a first gate 114a including a gate electrode 108 formed on the silicon substrate 102 and sidewalls...
US-8,143,151 Nanowire electronic devices and method for producing the same
The present invention is directed to an electrical device that comprises a first and a second fiber having a core of thermoelectric material embedded in an...
US-8,143,150 Method of fabricating semiconductor device and electronic system
A method of fabricating a semiconductor device includes forming a well impurity region, a lower impurity region and an upper impurity region in a semiconductor...
US-8,143,149 Method of forming a flexible nanostructured material for photovoltaic panels
An efficient and low-cost method is intended for forming a flexible nanostructured material suitable for use as an active element of a photovoltaic panel. The...
US-8,143,148 Self-aligned multi-dielectric-layer lift off process for laser diode stripes
A method for forming a laser diode structure. The method includes providing a laser diode material having a surface region. A multilayer dielectric mask...
US-8,143,147 Methods and systems for forming thin films
A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided,...
US-8,143,146 Method for manufacturing a nonvolatile storage device
A method for manufacturing a nonvolatile storage device with a plurality of unit memory layers stacked therein is provided. Each of the unit memory layers...
US-8,143,145 Method and arrangement for producing an N-semiconductive indium sulfide thin layer
A method of producing, at atmospheric pressure, an n-type semiconductive indium sulfide thin film on a substrate using an indium-containing precursor, hydrogen...
US-8,143,144 Semiconductor nanowire and its manufacturing method
A method for fabricating a semiconductor nanowire that has first and second regions is provided. A catalyst particle is put on a substrate. A first source gas...
US-8,143,143 Process for fabricating nanowire arrays
A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the...
US-8,143,142 Method of fabricating epi-wafer, epi-wafer fabricated by the method, and image sensor fabricated using the...
A method of fabricating an epi-wafer includes providing a wafer including boron by cutting a single crystal silicon ingot, growing an insulating layer on one...
US-8,143,141 Laser beam machining method and semiconductor chip
A laser processing method is provided, which, when cutting a substrate formed with a multilayer part including a plurality of functional devices, makes it...
US-8,143,140 Substrate having thin film of GaN joined thereon and method of fabricating the same, and a GaN-based...
There is provided a method of producing a thin GaN film-joined substrate, including the steps of: joining on a GaN bulk crystalline body a substrate different...
US-8,143,139 Method of fabricating extended drain MOS transistor
A method of fabricating an extended drain MOS transistor which reduces a design rule and prevents the generation of leakage current. The method includes...
US-8,143,138 Method for fabricating interconnect structures for semiconductor devices
Described herein are methods for fabricating dual-damascene interconnect structures. In one embodiment, the interconnect structures are fabricated with a...
US-8,143,137 Method of fabricating semiconductor device by thinning hardmask layers on frontside and backside of substrate
The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for...
US-8,143,136 Method for fabricating crown-shaped capacitor
A method for fabricating a crown-shaped capacitor includes providing a first dielectric layer with a protective pillar formed thereover, including a first...
US-8,143,135 Embedded series deep trench capacitors and methods of manufacture
Trench capacitors and methods of manufacturing the trench capacitors are provided. The trench capacitors are very dense series capacitor structures with...
US-8,143,134 Method for manufacturing SOI substrate
The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after...
US-8,143,133 Technique for enhancing dopant profile and channel conductivity by millisecond anneal processes
During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the...
US-8,143,132 Transistor including a high-K metal gate electrode structure formed on the basis of a simplified spacer regime
In sophisticated semiconductor devices, the threshold voltage adjustment of high-k metal gate electrode structures may be accomplished by a work function metal...
US-8,143,131 Method of fabricating spacers in a strained semiconductor device
The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy...
US-8,143,130 Method of manufacturing depletion MOS device
The present invention discloses a method of manufacturing a depletion metal oxide semiconductor (MOS) device. The method includes: providing a substrate;...
US-8,143,129 Integration of non-volatile charge trap memory devices and logic CMOS devices
A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed...
US-8,143,128 Multilayer dielectric defect method
A method forms a first inorganic dielectric layer having a first concentration of defects and a second inorganic dielectric layer in contact with a first layer...
US-8,143,127 Semiconductor device having asymmetric bulb-type recess gate and method for manufacturing the same
A semiconductor device includes a silicon substrate; a device isolation structure formed in the silicon substrate to delimit an active region which has a pair...
US-8,143,126 Method for forming a vertical MOS transistor
A method is used to form a vertical MOS transistor. The method utilizes a semiconductor layer. An opening is etched in the semiconductor layer. A gate...
US-8,143,125 Structure and method for forming a salicide on the gate electrode of a trench-gate FET
A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric...
US-8,143,124 Methods of making power semiconductor devices with thick bottom oxide layer
A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom includes forming a drift...
US-8,143,123 Methods of forming inter-poly dielectric (IPD) layers in power semiconductor devices
A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate...
US-8,143,122 Nonvolatile semiconductor memory and method of manufacturing the same
A nonvolatile semiconductor memory includes a first and a second diffusion layer regions, a floating gate electrode disposed, with a gate insulating film...
US-8,143,121 DRAM cell with double-gate fin-FET, DRAM cell array and fabrication method thereof
A transistor structure includes a semiconductor substrate having a top surface and sidewalls extending downward from the top surface, wherein each of the...
US-8,143,120 Multiple doping level bipolar junctions transistors and method for forming
A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated...
US-8,143,119 Method of manufacturing semiconductor device having plural transistors formed in well region and semiconductor...
A first transistor and a second transistor are formed in a first element formation region, and a third transistor is formed in a second element formation...
US-8,143,118 TFT device with channel region above convex insulator portions and source/drain in concave between convex...
A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a...
US-8,143,117 Active device array substrate and method for fabricating the same
A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive...
US-8,143,116 Thin film transistor array substrate and manufacturing method thereof
A thin film transistor array substrate includes a gate line disposed on a substrate, the gate line comprising a gate electrode including a lower film and an...
US-8,143,115 Method for manufacturing thin film transistor using oxide semiconductor and display apparatus
A thin film transistor is manufactured by forming a gate electrode on a substrate, forming a first insulating film on the gate electrode, forming an oxide...
US-8,143,114 System and method for source/drain contact processing
System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a...
US-8,143,113 Omega shaped nanowire tunnel field effect transistors fabrication
A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the...
US-8,143,112 Method for removing semiconductor street material
Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface...
US-8,143,111 System and method for configuring an integrated circuit
A system and method for configuring an integrated circuit. Embodiments include a method for manufacturing an integrated circuit (IC), comprising associating...
US-8,143,110 Methods and apparatuses to stiffen integrated circuit package
A dam stiffener for a package substrate is presented. In an embodiment, the dam stiffener comprises a thermally curable polymer, and is simultaneously cured...
US-8,143,109 Method for fabricating damascene interconnect structure having air gaps between metal lines
An exemplary method for fabricating a damascene interconnect structure includes the following. First, providing a substrate. Second, depositing a multilayer...
US-8,143,108 Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate
A semiconductor device has a first substrate with a central region. A plurality of bumps is formed around a periphery of the central region of the first...
US-8,143,107 Integrated circuit packaging system substrates and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: forming a substrate including: patterning a bonding pad on the substrate, patterning...
US-8,143,106 Thermosetting die-bonding film
The thermosetting die-bonding film of the present invention is used in manufacturing a semiconductor device, has at least an epoxy resin, a phenol resin, and an...
US-8,143,105 Semiconductor seal ring and method of manufacture thereof
An improved semiconductor seal ring and method therefore is described. The seal ring comprises a thick layer wherein at least a portion of the thick layer is...
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