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Patent # Description
US-8,149,660 Drive apparatus, method of informing possibility of handling and operating recording medium, control method of...
A drive apparatus that handles and operates a recording medium attached with a memory tag, the drive apparatus include: a recording medium mounting part on...
US-8,149,659 Recording and/or reproducing apparatus, recording and/or reproducing method and information storage medium therefor
A recording and/or reproducing apparatus, a recording and/or reproducing method, and an information storage medium, wherein the recording and/or reproducing...
US-8,149,658 Method of erasing data from optical disc
A method and device for erasing data from an optical disc, are discussed. In an embodiment of the present invention, the area of the optical disc where data has...
US-8,149,657 Optical waveguide clad material
An apparatus includes a waveguide having a core layer and first and second cladding layers on opposite sides of the core layer, wherein the cladding layers...
US-8,149,656 Switch device, information processing device, and reproduction device
A reproduction system 100 includes a rotating body on which a rotary operation is conducted by a user, a rotary movement detector 810 that detects the rotation...
US-8,149,655 Information recording medium, information recording apparatus and method, information reproducing apparatus and...
An information recording medium (100), provided with: a first recording layer (L0 layer) and a second recording layer (L1 layer) in each of which record...
US-8,149,654 Wave guide that attenuates evanescent light of higher order TM mode
A waveguide has a core through which laser light can propagate in a TM mode, that has a rectangular cross section perpendicular to a propagative direction of...
US-8,149,653 Light source unit for thermally-assisted magnetic recording capable of monitoring of light output
Provided is a light source unit that is to be joined to a slider to form a thermally-assisted magnetic recording head. The light source unit comprises: a unit...
US-8,149,652 Compensating the effects of static head-media spacing variations and nonlinear transition shift in heat...
An apparatus comprises a storage medium, a recording head, a source of electromagnetic radiation, and a control circuit for modulating the source of...
US-8,149,651 Resonator mounted in a case incorporating a watch module
The invention concerns an electronic watch comprising an electric motor (5) for driving analogue display means (6), and a time base (1, 2) comprising an...
US-8,149,650 Wearable electronic device with secondary digital display
A wearable electronic device of the type wherein information is conveyed in an analog manner at least in part by the use of at least one display hand, wherein...
US-8,149,649 Self calibrating shooter estimation
Disclosed are systems and methods that can be used to detect shooters. The systems and methods described herein use arrival times of a shockwave, produced by a...
US-8,149,648 Method of processing echo pulses, and pulse-echo ranging system using the method
Error correction in an echo pulse is performed by periodically (for example, every 100th pulse) generating a parabola derived from a selected part of the pulse...
US-8,149,647 Seismic cable and acoustically decoupled sensor
A robust seismic cable and sensor module system wherein the sensor modules include a housing and sensing unit. The housing substantially transfers the load and...
US-8,149,646 Digital filters for semiconductor devices
A memory device that, in certain embodiments, includes a memory element and a digital filter. The digital filter may include a counter and a divider, where the...
US-8,149,645 Synchronous global controller for enhanced pipelining
The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and...
US-8,149,644 Memory system and method that changes voltage and frequency
The memory system includes a semiconductor memory that has an internal circuit, which operates according to a first power supply voltage, and a memory...
US-8,149,643 Memory device and method
A memory device and method may include separating alternating read and write accesses to different banks of a memory device.
US-8,149,642 Semiconductor memory device
A semiconductor memory device includes a first power switch for interrupting supply of a first power voltage to a first node in a standby mode, and a second...
US-8,149,641 Active cycle control circuit for semiconductor memory apparatus
An active cycle control circuit for a semiconductor memory apparatus is configured to precharge a word line corresponding to a read cycle, and activate a word...
US-8,149,640 Differential sense amplifier
The differential sense amplifier according to one aspect of the present invention includes a first differential amplification unit that detects a difference...
US-8,149,639 Test apparatus of semiconductor integrated circuit and method using the same
A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse...
US-8,149,638 Semiconductor memory device and inspecting method of the same
According to one embodiment, a semiconductor memory device includes a memory cell array includes memory cells, lines provided to correspond to the memory cells,...
US-8,149,637 Semiconductor device capable of being tested after packaging
Provided is a semiconductor device capable of effectively testing whether memory cells and a memory cell array are defective. The semiconductor device may...
US-8,149,636 Semiconductor memory device with pulse width determination
A semiconductor memory device includes a reset signal generating unit configured to generate a reset control signal by delaying a column command signal by an...
US-8,149,635 Non-volatile memory device and program method thereof
A non-volatile memory device including a memory cell array; a read/write circuit configured to drive bit lines of the memory cell array with a negative bit line...
US-8,149,634 Low power memory architecture
A memory architecture and circuits for minimizing current leakage in the memory array. Subdivisions of the memory array each have local power grids that can be...
US-8,149,633 Semiconductor memory device
A semiconductor memory device is provided which includes a voltage detecting unit configured to compare a target voltage level with a fed-back internal voltage...
US-8,149,632 Output circuit for a semiconductor memory device and data output method
An outputting transistor circuit of a push-pull structure has an outputting PMOS transistor and an outputting NMOS transistor connected in series between a...
US-8,149,631 Non-volatile semiconductor storage device
For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an...
US-8,149,629 Semiconductor storage device adapted to prevent erroneous writing to non-selected memory cells
A memory cell array has a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells...
US-8,149,628 Operating method of non-volatile memory device
A non-volatile memory device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the...
US-8,149,627 Current sink system based on sample and hold for source side sensing
Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current...
US-8,149,626 Threshold voltage digitizer for array of programmable threshold transistors
A method and system for determining a respective threshold voltage of each of a plurality of transistors in a memory array. The method includes: applying a ramp...
US-8,149,625 Nonvolatile memory device, operating method thereof, and memory system including the same
A nonvolatile memory device includes a memory cell array; a voltage generator configured to provide stepwise increasing step pulses for varying logic states of...
US-8,149,624 Method and apparatus for reducing read disturb in memory
Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution--a version with a reduced maximum, and another version....
US-8,149,623 Controller and non-volatile semiconductor memory device
A controller includes a generation unit configured to aggregate comparison results between second threshold voltage levels held in the memory cells and...
US-8,149,622 Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and...
A memory system includes a NAND flash memory, a NOR flash memory and a SRAM memory on a single chip. Both NAND and NOR memories are manufactured by the same...
US-8,149,621 Flash memory device and method of testing the flash memory device
A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a...
US-8,149,620 Flash memory device having dummy cell
A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells...
US-8,149,619 Memory structure having volatile and non-volatile memory portions
A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active...
US-8,149,618 Over-sampling read operation for a flash memory device
A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a...
US-8,149,617 Data storage medium and method for accessing digital data therein
A data storage medium is described. The data storage medium may comprise a first bit of magnetic medium for a first read-and-write head, and further comprise a...
US-8,149,616 Method for multilevel programming of phase change memory cells using adaptive reset pulses
A method for programming multilevel PCM cells envisages: forming an amorphous region of amorphous phase change material in a storage element of a PCM cell by...
US-8,149,615 Magnetic random access memory
An MRAM has: a memory cell including a first magnetoresistance element; and a reference cell including a second magnetoresistance element. The first...
US-8,149,614 Magnetoresistive random access memory element and fabrication method thereof
A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first...
US-8,149,613 Resistance variable memory device
A resistance variable memory device is provided and includes a resistance variable memory cell that writes data by utilizing a spin transfer effect based on an...
US-8,149,612 Memory array and method of implementing a memory array
A memory array having a plurality of memory cells is disclosed, where each memory cell comprises a first inverter having a first transistor coupled between a...
US-8,149,611 Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable...
US-8,149,610 Nonvolatile memory device
A memory device comprises an array of memory cells each capable of storing multiple bits of data. Each memory cell includes a programmable transistor in series...
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