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Patent # Description
US-8,161,468 Processing of expressions
In many messaging systems, message selection filtering involves a significant processing overhead. This includes the parsing and preparing of the message...
US-8,161,467 Compiling method and storage medium therefor
A compiler includes a register allocator for allocating registers for instructions in a program to be compiled, and a code generator for generating object code...
US-8,161,466 Method of pre-processing conditional region
Provided is a method of pre-processing a conditional region. By analyzing and designating code lines according to the present invention, when a conditional...
US-8,161,465 Method and apparatus for performing conditional compilation
One embodiment of the present invention provides a system that facilitates performing conditional compilation. The system operates by analyzing programming...
US-8,161,464 Compiling source code
A method of compiling source code. The method includes converting pointer-based access in the source code to array-based access in the source code in a first...
US-8,161,463 System and method of interlocking to protect software--mediated program and device behaviors
A method for rendering software resistant to reverse engineering. Replace at least one first constant (mathematical expression, etc.) in a computational...
US-8,161,462 Program-level performance tuning
A method, apparatus, system, and signal-bearing medium that in an embodiment request a program or programs to tune themselves to run faster or slower if a...
US-8,161,461 Systems and methods for evaluating code usage
In one embodiment, a method for evaluating code usage includes monitoring instructions executed by a processor, counting instances of execution of each...
US-8,161,460 System and method of automatic interoperability checking for BPEL
In one embodiment the present invention includes a method of determining whether computer processes can interact without deadlocks. The computer processes may...
US-8,161,459 Method and system for generating functional test cases
The present invention provides a method, system and computer program product for generating one or more functional test cases for testing a software...
US-8,161,458 Method and apparatus to increase efficiency of automatic regression in "two dimensions"
Techniques for efficiently isolating software regressions are provided. A system test tool determines that a particular regression is present in a particular...
US-8,161,457 Detection of errors caused by interactions of independent software vendor code with host code
A method is provided for isolating errors which occur when code supplied by independent software vendors (ISV code) interacts with code supplied by a primary...
US-8,161,456 Management of heterogeneous software artifacts through a common representation
A method for managing a configuration of heterogeneous software artifacts through a common central configuration representation includes adding a plurality of...
US-8,161,455 Concurrent execution of multiple primitive commands in command line interface
A method to concurrently execute multiple primitive commands in a command line interface (CLI) is provided. Each of a plurality of signal parameters is...
US-8,161,454 Software architecture for developing in-vehicle software applications
According to one embodiment of the present invention, a software architecture encoded on a computer readable medium is disclosed. The software architecture can...
US-8,161,453 Method and apparatus for implementing task management of computer operations
A development and runtime framework for applications that execute in real-time operating systems. Application development is enhanced through simple...
US-8,161,452 Software cinema
The invention comprises a system and method for employing video in development processes. A new theory of operation for mapping video to formal models is...
US-8,161,451 PWB voltage and/or current calculation and verification
Disclosed is a layout tool that verifies the operability of a printed circuit board design. Electrical parameters may be calculated for wire traces that are...
US-8,161,450 Re-programmable modular power management circuit
An integrated circuit includes a buck converter controller, a PFET, an NFET that is coupled in common drain configuration to the PFET, a first microbump that is...
US-8,161,449 Improving test pattern coverage through parallel discard, flow control, and quality metrics
A method, computer program product, and data processing system that controls test packets that are sent to a coordinating computer system is provided. A node...
US-8,161,448 Replicant simulation
In one embodiment, a method comprises partitioning a circuit description into a plurality of simulateable partitions. The partitioning is independent of a...
US-8,161,447 Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage
A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit...
US-8,161,446 System and method of connecting a macro cell to a system power supply
A system and method of connecting a macro cell to a system power supply network is disclosed. In a particular embodiment, the method includes determining a...
US-8,161,445 Logic transformation and gate placement to avoid routing congestion
A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from...
US-8,161,444 Allocating hardware resources for high-level language code sequences
Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences or subroutines provided in a high-level...
US-8,161,443 System for analyzing sensitivity of parasitic capacitance to variation of semiconductor design parameters
A sensitivity analysis system has a memory device in which an interconnect structure data indicating an interconnect structure included in a semiconductor...
US-8,161,442 Integrated circuit devices and methods and apparatuses for designing integrated circuit devices
Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference...
US-8,161,441 Robust scan synthesis for protecting soft errors
A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled...
US-8,161,440 Highly specialized scenarios in random test generation
A computer software product is provided. The product includes a computer-readable medium in which computer program instructions are stored, which instructions,...
US-8,161,439 Method and apparatus for processing assertions in assertion-based verification of a logic design
Method and apparatus for processing assertions in assertion-based verification of a logic design are described. One example relates to processing an assertion...
US-8,161,438 Determining mutual inductance between intentional inductors
Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design...
US-8,161,437 Method and apparatus for automated synthesis of multi-channel circuits
Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present...
US-8,161,436 Method and system for transforming fork-join blocks in a hardware description language (HDL) specification
The present invention provides a method, system and article of manufacture for the transformation of parallel blocks into synchronized parallel processes that...
US-8,161,435 Reset mechanism conversion
Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described....
US-8,161,434 Statistical formal activity analysis with consideration of temporal and spatial correlations
Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one...
US-8,161,433 Utilizing an unSAT proof for model checking
A proof of unsatisfiability associated with a bounded model may be extended to apply to another bounded model having a larger bound. In some exemplary...
US-8,161,432 Automated processor generation system and method for designing a configurable processor
A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only...
US-8,161,431 Integrated circuit performance enhancement using on-chip adaptive voltage scaling
Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance...
US-8,161,430 System and method of resistance based memory circuit parameter adjustment
Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of...
US-8,161,429 Methods and apparatus for initializing serial links
A serial communications protocol is provided that has optional link initialization features such as an optional automatic lane polarity reversal feature and an...
US-8,161,428 Method of predicting reliability of semiconductor device, reliability prediction system using the same and...
An initial reliability of a semiconductor device is predicted before the design layout of a semiconductor product. A method of predicting the reliability of a...
US-8,161,427 Logic circuit and method of logic circuit design
A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first...
US-8,161,426 Method and system for sizing polygons in an integrated circuit (IC) layout
One embodiment of the present invention provides a system that sizes a polygon in a layout. During operation, the system receives a polygon which is to be sized...
US-8,161,425 Method and system for implementing timing aware metal fill
An improved approach for implementing metal fill on an electrical device without causing creating cross-coupling capacitance problems is disclosed. Timing aware...
US-8,161,424 Method and apparatus for modeling chemically amplified resists
Some embodiments provide a system for accurately and efficiently modeling chemically amplified resist. During operation, the system can determine a quenched...
US-8,161,423 Defect filtering optical verification process
An apparatus and method for optical lithography verification includes filtering a lithography simulation of proposed sub-lightwave pattern formations during at...
US-8,161,422 Fast and accurate method to simulate intermediate range flare effects
A method is provided for modeling lithographic processes in the design of photomasks for the manufacture of semiconductor integrated circuits, and more...
US-8,161,421 Calibration and verification structures for use in optical proximity correction
A method of training an Optical Proximity Correction (OPC) model comprises symmetrizing a complex design to be a test pattern having orthogonal symmetry....
US-8,161,420 System and method for security management of home network
A security management system of a home network is provided. The home network includes a home gateway and one or more user devices connected to the home gateway....
US-8,161,419 Integrated graphical user interface and system with focusing
An integrated web-based communications/calendar/organizational/entertainment system provides a user interface to provide the most pertinent data to a user at...
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