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Patent # Description
US-8,159,914 Information-recording system including error detection and a data recording position adjustment unit and...
[Object] To Reduce Read Errors. [Solving Means] Where new data recording is started from LRA (old) and a record error is detected, at position P0, an extent is...
US-8,159,913 Optical disc recording apparatus and recording power control method
It is to provide an optical disc recording apparatus and a recording power control method that are adapted to high-speed recording and can set an optimal...
US-8,159,912 Recording parameter setting device, program thereof, computer-readable recording medium containing the program,...
A recording parameter setting device including a trial recording parameter setting section and a reproduced signal quality judging section. The reproduced...
US-8,159,911 Recording device, recording method, disc manufacturing method and optical disc recording medium
An optical disc recording medium is irradiated with laser light having a predetermined laser power to deform an irradiated portion of a substrate into a...
US-8,159,910 Apparatus and method for controlling tracking error balance in optical disc apparatus
A method of controlling a tracking error balance in an optical disc apparatus, and the optical disc apparatus are discussed. In an embodiment of the present...
US-8,159,909 Optical head, optical drive apparatus, and method for generating tracking error signal
An optical head that includes a laser light source, an optical system that applies 0-order diffracted light, +1-order diffracted light, and -1-order diffracted...
US-8,159,908 Photo diode ic
A photodetector detecting reflected light components from an optical medium, the photodetector including a first detector divided into eight sections detecting...
US-8,159,907 Optical pickup device
An optical pickup device includes a photodetector which receives laser light reflected on a recording medium, and an optical system which guides laser light to...
US-8,159,906 Address generating and detecting method and reproducing and recording apparatus
Recording capacity per layer is detected from a disc and bit allocation of wobble addresses in a conventional optical disc and bit allocation in a high-density...
US-8,159,905 Portable telephone provided with a mechanical watch
Portable device, of all types, comprising a watch (1) with mechanical winding, characterized in that a mechanical device doing away with the need for the user...
US-8,159,904 Force-feedback seismometer
A broadband weak-motion seismometer includes: a frame, a mass, a suspension means for movably connecting the mass to the frame, a sensing transducer for...
US-8,159,903 Underwater communication system
Underwater communication system comprising a plurality of communication modules, each provided with a microprocessor, a memory, a transmitter and a receiver...
US-8,159,902 Apparatus and method for localizing sound source in robot
An apparatus and method for localizing a sound source in a robot are provided. The apparatus includes a microphone unit implemented by one or more microphones,...
US-8,159,901 System and method for discriminating a subsurface target in the water from a surface target in the water
A computer-implemented method of discriminating a surface from a subsurface sound-generating target in the water includes identifying an arrival angle of sound...
US-8,159,900 Acoustic system quality assurance and testing
Embodiments of the invention provide systems and methods for testing acoustic systems. According to one embodiment, a method for testing an acoustic system can...
US-8,159,899 Wordline driver for memory
Subject matter disclosed herein relates to accessing memory, and more particularly to a wordline driver of same.
US-8,159,898 Architecture of highly integrated semiconductor memory device
A semiconductor memory device includes: a first row control circuit region corresponding to a first memory bank; a first column control circuit region...
US-8,159,897 Two levels of voltage regulation supplied for logic and data programming voltage of a memory device
Systems and methods involve the use of a flash memory device having multiple flash memory cells. A first interface is adapted to receive power for selectively...
US-8,159,896 Local power domains for memory sections of an array of memory
Memories, memory arrays, and methods for selectively providing electrical power to memory sections of a memory array are disclosed. A memory array can be...
US-8,159,895 Method and system for split threshold voltage programmable bitcells
Methods and systems for split threshold voltage programmable bitcells are disclosed and may include selectively programming bitcells in a memory device by...
US-8,159,894 One time programmable memory
A one-time programmable memory. The one-time programmable memory has an antifuse and a read circuit configured to read the antifuse. An isolation transistor...
US-8,159,893 Data flow control in multiple independent port
A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory...
US-8,159,892 Nonvolatile memory device and method of testing the same
A nonvolatile memory device includes a storage unit configured to store pattern data selected based on a test command set, and a control unit configured to...
US-8,159,891 Sensing characteristic evaluating apparatus for semiconductor device and method thereof
A sensing characteristic evaluating apparatus for a semiconductor device includes a test current supply unit configured to supply a test current to an...
US-8,159,890 Redundant memory array for replacing memory sections of main memory
Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory...
US-8,159,889 Solid state disk controller apparatus
A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus;...
US-8,159,888 Recalibration systems and techniques for electronic memory applications
A memory circuit includes a delay module receiving a strobe signal and producing a delayed strobe signal therefrom. The memory circuit also includes a...
US-8,159,887 Clock synchronization in a memory system
A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at...
US-8,159,886 Memory device, control method for the same, control program for the same, memory card, circuit board and...
A memory device having a single or a plurality of memory chips includes a memory part (control register, SPD memory unit) inside each memory chip, which memory...
US-8,159,885 Refresh control circuit and semiconductor memory device and memory system including the same
A semiconductor memory device includes a refresh control circuit and a memory cell array. The refresh control circuit generates an internal auto refresh control...
US-8,159,884 Nonvolatile semiconductor memory device
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor, a word line, a row decoder, a sense amplifier which...
US-8,159,883 Semiconductor memory device having a block decoder for preventing disturbance from unselected memory blocks
A semiconductor memory device can improve electrical properties by prohibiting a leakage current, which flows through a memory cell, in such a way as to turn...
US-8,159,882 Nonvolatile semiconductor memory device and memory system
A semiconductor memory device executes a writing operation based on a first bit assignment pattern at the time of writing. The first bit assignment pattern is...
US-8,159,881 Reference voltage optimization for flash memory
A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory...
US-8,159,880 NAND flash memory
In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell...
US-8,159,879 Reducing effects of program disturb in a memory device
A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on...
US-8,159,878 Semiconductor memory having both volatile and non-volatile functionality and method of operating
Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a...
US-8,159,877 Method of directly reading output voltage to determine data stored in a non-volatile memory cell
An NVM cell design enables direct reading of cell output voltage to determine data stored in the cell, while providing low current consumption and a simple...
US-8,159,876 Non-volatile memory and method for power-saving multi-pass sensing
A non-volatile memory device and power-saving techniques capable of reading and writing a large number of memory cells with multiple read/write circuits in...
US-8,159,875 Methods of storing multiple data-bits in a non-volatile memory cell
Methods of storing multiple data-bits in a non-volatile memory cell are carried out by trapping carriers in a composite trapping layer formed over a tunnel...
US-8,159,874 Cell operation monitoring
Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data...
US-8,159,873 Semiconductor integrated circuit
There is provided a semiconductor integrated circuit including a state detection enhancement circuit which includes an input terminal and an output terminal and...
US-8,159,872 Magnetic random access memory
An MRAM has: a memory cell including a first magnetoresistance element; and a reference cell including a second magnetoresistance element. The first...
US-8,159,871 Magnetoresistive memory cell using floating body effect, memory device having the same, and method of operating...
A magnetoresistive memory cell includes an MTJ device and a select transistor. The select transistor includes a first conduction-type semiconductor layer, a...
US-8,159,870 Array structural design of magnetoresistive random access memory (MRAM) bit cells
Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a...
US-8,159,869 Circuit and method for generating reference voltage, phase change random access memory apparatus and read...
A circuit for generating a reference voltage includes at least one reference cell, a reference cell write driver, a reference cell sense amplifier, and a...
US-8,159,868 Semiconductor memory having both volatile and non-volatile functionality including resistance change material...
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein...
US-8,159,867 Phase change memory devices and systems, and related programming methods
A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored...
US-8,159,866 Method and system for providing dual magnetic tunneling junctions usable in spin transfer torque magnetic memories
A method and system for providing a magnetic junction usable in a magnetic memory are described. The magnetic junction includes first and second pinned layers,...
US-8,159,865 Information storage element and method of writing/reading information into/from information storage element
In a method of writing information into and reading information from an information storage element which includes a strip-shaped ferromagnetic material layer,...
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