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| Patent # | Description |
|---|---|
| US-8,159,314 |
Actively tuned filter An actively tuned filter providing a constant bandwidth at a plurality of frequencies. The filter includes first and second electromagnetically coupled coiled... |
| US-8,159,313 |
Systems, methods, and apparatus for electrical filters and input/output
systems An electronic filtering device includes continuous trace on a dielectric substrate and a dissipation layer communicatively coupled to the trace. The dissipation... |
| US-8,159,312 |
Method and system for signal coupling and direct current blocking A method and class of circuit configurations for coupling low-frequency signals from one stage of an electronic apparatus to another stage, from the outside... |
| US-8,159,311 |
High frequency package and manufacturing method thereof A high frequency package in which the resonance frequency of a metal seal ring is high, a reflection loss and a insertion loss of an input terminal and an... |
| US-8,159,310 |
Mictostrip transmission line structure with vertical stubs for reducing
far-end crosstalk Provided is a microstrip transmission line for reducing far-end crosstalk. In a conventional microstrip transmission line on a printed circuit board, a... |
| US-8,159,309 |
Windowing to narrow a bandwidth of an amplitude modulation power supply
input signal The present disclosure relates to using windowing to reduce the bandwidth of an amplitude modulation (AM) power supply input signal (PSIS), which is fed to an... |
| US-8,159,308 |
Low power voltage controlled oscillator (VCO) An apparatus includes a tank circuit of a voltage controlled oscillator (VCO). A pair of alternating current (AC) coupling capacitors couple the gates of the... |
| US-8,159,307 |
Logical element In a logical element, supporting portions, and a beam supported by them at two ends are formed. The beam has a back side surface spaced apart from the top side... |
| US-8,159,306 |
Integrated circuit with low temperature coefficient and associated
calibration method An integrated circuit (IC) with a low temperature coefficient and an associated calibration method are provided to lower the effect of the environmental... |
| US-8,159,305 |
Amplifying device An amplifying device includes a selecting section that selects one of a first power source potential and a second power source potential which are different... |
| US-8,159,304 |
Apparatus and method for feed-forwarding in a current-feedback amplifier A current-feedback amplifier with at least one feed-forward capacitor at the input stage of the current-feedback amplifier is provided. In one embodiment, the... |
| US-8,159,303 |
Operational amplifier An operational amplifier includes an input stage amplifier that receives an input signal, an output stage amplifier that amplifies a signal output from the... |
| US-8,159,302 |
Differential amplifier circuit A differential amplifier circuit includes: P-type and N-type differential input units outputting respectively first and second outputs in response to first and... |
| US-8,159,301 |
Differential amplifier with hysteresis An amplifier circuit having a differential input and an amplifier output is provided. In some examples, the amplifier circuit includes a first input stage... |
| US-8,159,300 |
Signal conversion circuit and rail-to-rail circuit A signal conversion circuit 2 according to an embodiment of the present invention has a difference amplifier 10 and a source follower 20. The difference... |
| US-8,159,299 |
Duplicate feedback network in class D amplifiers A circuit and a method are provided for suppressing the pop and click noise during the power on and power off of Class D amplifiers. The technique also... |
| US-8,159,298 |
Linearization circuits and methods for power amplification Linearization circuits of the invention are used in conjunction with power amplification circuits that comprise a power amplifier core. Exemplary linearization... |
| US-8,159,297 |
Transmission device, distortion compensation device, and distortion
compensation method A transmission device includes an amplifier that amplifies a transmission signal according to a voltage to be applied, an envelope detector that detects an... |
| US-8,159,296 |
Method and apparatus for a power supply modulator linearizer A method and apparatus for a power amplifier module is described. The module includes a power amplifier and a power supply modulator coupled to the power... |
| US-8,159,295 |
Supply-modulated RF power amplifier and RF amplification methods An embodiment of the invention is a method of generating a reduced bandwidth envelope signal V.sub.DD(t) for the power supply modulator of an RF amplifier. An... |
| US-8,159,294 |
Multi-voltage headphone drive circuit The present invention discloses a multi-voltage headphone driver circuit comprising: at least one operational amplifier having an output supplied to a headphone... |
| US-8,159,293 |
Nested transimpendance amplifier A nested transimpedance amplifier circuit including a first power source, a second power source, a charge pump module and a transimpedance amplifier. The first... |
| US-8,159,292 |
Amplifying circuit To efficiently obtain two outputs including one at a normal level and the other at an excessive level. An input signal input to the negative input terminal of... |
| US-8,159,291 |
AM (amplitude modulation) demodulation system for RFID reader device An RFID reader device (31), of the type comprising a demodulator (6) for receiving from a RFID tag (11) an AM (Amplitude Modulation) wave (20) having a... |
| US-8,159,290 |
Test apparatus, demodulation apparatus, test method, demodulation method
and electric device Provided is a test apparatus for testing a device under test that outputs, as an output signal, an amplitude-phase modulated signal having a level and a... |
| US-8,159,289 |
Chip card having an adjustable demodulation unit The present invention shows a contactless chip card comprising a controllable demodulation unit for demodulating an amplitude-modulated carrier signal, a... |
| US-8,159,288 |
Low power BPSK demodulator A low power BPSK demodulator having a simple architecture, compact design and reliable is provided. The BPSK demodulator includes a first branch (210) having a... |
| US-8,159,287 |
Transistor device and method A field-effect transistor device, including: a semiconductor heterostructure comprising, in a vertically stacked configuration, a semiconductor gate layer... |
| US-8,159,286 |
System and method for time-to-voltage conversion with lock-out logic An event time stamping system comprising a current source, an integrator comprising an input and an output, and configured to output a voltage proportional to... |
| US-8,159,285 |
Current supply circuit A current supply circuit according to an embodiment of the present invention includes an operational amplifier having first and second input terminals and an... |
| US-8,159,284 |
Method for regulating temperature and circuit therefor A method and circuit for managing thermal performance of an integrated circuit. In accordance with an embodiment, a thermal limit circuit and a semiconductor... |
| US-8,159,283 |
High frequency switch circuit comprising a transistor on the high
frequency path A high frequency switch circuit according to the present invention includes a control-voltage-generating circuit. The control-voltage-generating circuit... |
| US-8,159,282 |
Semiconductor integrated circuit and high frequency module with the same The present invention is directed to reduce increase in the level of a harmonic signal of an RF (transmission) Tx output signal at the time of supplying an RF... |
| US-8,159,281 |
Method and device for delaying activation timing of output device A delay method for determining an activation moment of an output device in a circuit system is disclosed. The delay method includes determining resistance of an... |
| US-8,159,280 |
Noise generator A noise generator for generating band-limited noise from a plurality of sinusoidal signals at the same level and equidistant frequency position in the noise... |
| US-8,159,279 |
Current driving circuit In current driving circuit a desired value of a driving current is promptly written in a load of each pixel despite load variations that may occur in each... |
| US-8,159,278 |
Method for clamping a semiconductor region at or near ground A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current... |
| US-8,159,277 |
Techniques for providing multiple delay paths in a delay circuit A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The... |
| US-8,159,276 |
Method for using digital PLL in a voltage regulator A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage... |
| US-8,159,275 |
Phase-locked loop and bias generator A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a... |
| US-8,159,274 |
Signaling with superimposed clock and data signals A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission... |
| US-8,159,273 |
Transmission circuit A transmission circuit including a first circuit outputting a first signal based on an input data, a second circuit outputting a second signal based on the... |
| US-8,159,272 |
System and method for on-chip jitter and duty cycle measurement An apparatus for measuring time interval between two selected edges of a clock signal. includes an edge generator, a first multi-tap delay module, a second... |
| US-8,159,271 |
Scan driver A scan driver includes a voltage setting circuit, a counter circuit, a logic circuit, a dynamic decoder, N level shift circuits and N output stage circuits,... |
| US-8,159,270 |
Circuitry and methods minimizing output switching noise through
split-level signaling and bus division enabled... Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The... |
| US-8,159,269 |
Multi-function input terminal of integrated circuits A single terminal is used to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and... |
| US-8,159,268 |
Interconnect structures for metal configurable integrated circuits Interconnect structure comprising buffers for a semiconductor device is disclosed. The buffer comprises: an input and an output; and a programmable interconnect... |
| US-8,159,267 |
Semiconductor device, display device, and electronic device To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics;... |
| US-8,159,266 |
Metal configurable integrated circuits A metal programmable semiconductor device is disclosed. The semiconductor device, comprises: a metal programmable logic circuit; and a plurality of fixed... |
| US-8,159,265 |
Memory for metal configurable integrated circuits Memory for a semiconductor device is disclosed. The memory array comprises: a memory cell replicated in rows and columns to form an array; and a plurality of... |
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