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| Patent # | Description |
|---|---|
| US-8,161,368 |
Distributed processing when editing an image in a browser Methods, apparatus, computer program products and systems are provided for editing an image. In one method a selection of an image for editing is received at a... |
| US-8,161,367 |
Correction of single event upset error within sequential storage circuitry
of an integrated circuit Sequential storage circuitry includes first and second storage elements storing first and second indications of input data values received by the circuitry... |
| US-8,161,366 |
Finite state machine error recovery A method and system for using a magnitude comparator circuit and a flag bit, for detecting and preventing errors from occurring in the FSM state bits that could... |
| US-8,161,365 |
Cyclic redundancy check generator A cyclic redundancy check ("CRC") generator and method therefor are described. Checksum bits and checksum enable bits are bitwise ANDed to provide interim... |
| US-8,161,364 |
Out of order checksum calculation for fragmented packets A network interface controller comprises a first interface that sequentially receives second and first fragments of a packet comprising second and first data... |
| US-8,161,363 |
Apparatus and method to encode/decode block low density parity check codes
in a communication system An apparatus and method to encode a block Low Density Parity Check (LDPC) code in a signal transmission apparatus is disclosed. The method includes generating a... |
| US-8,161,362 |
Task management control apparatus and method, having redundant processing
comparison Processed results are received when processors make compatible computations on data of a common object. A computation command signal is generated and fed to the... |
| US-8,161,361 |
Averaging signals to improve signal interpretation Systems and techniques to interpret signals on a noisy channel. In general, in one implementation, the technique includes: interpreting an input signal as... |
| US-8,161,360 |
Integrated interleaved codes Integrated interleaved encoding is performed by obtaining a first piece of input data and a second piece of input data. The first piece of input data is... |
| US-8,161,359 |
System and method for generating a cyclic redundancy check A cyclic redundancy check generator includes a plurality of shift registers, each shift register corresponding to a coefficient of a general polynomial key... |
| US-8,161,358 |
Parity bit soft estimation method and apparatus The systematic and parity bits of a symbol are tightly coupled to each other based on the way in which the symbol is encoded. The relationship between the... |
| US-8,161,357 |
Systems and methods for using intrinsic data for regenerating data from a
defective medium Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that... |
| US-8,161,356 |
Systems, methods, and apparatuses to save memory self-refresh power Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some... |
| US-8,161,355 |
Automatic refresh for improving data retention and endurance
characteristics of an embedded non-volatile memory... A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to... |
| US-8,161,354 |
Flash memory controller having configuring unit for error correction code
(ECC) capability and method thereof A flash memory controller includes a control unit, a buffer, an error correction code (ECC) module, and a configuring unit. The flash memory has a data area for... |
| US-8,161,353 |
Apparatus, system, and method for validating that a correct data segment
is read from a data storage device An apparatus, system, and method are disclosed for validating that correct data is read from a storage device. A read request receiver module receives a read... |
| US-8,161,352 |
Method for providing unequal error protection to data packets in a burst
transmission system The present invention relates to a method for providing an equal error protection to data packets in a burst transmission system. The data packets are grouped... |
| US-8,161,351 |
Systems and methods for efficient data storage Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage... |
| US-8,161,350 |
Method and system for encoding a data sequence A communication method and a communication system including a first entity (3) including an information source (9) and a coder device (11) connected by a... |
| US-8,161,349 |
Data parallelizing receiver Provided is a data parallelizing receiver including an input signal receiver for externally receiving serial data as packets, sampling the serial data, aligning... |
| US-8,161,348 |
Systems and methods for low cost LDPC decoding Various embodiments of the present invention provide systems and circuits that provide for LDPC decoding and/or error correcting. For example, various... |
| US-8,161,347 |
Interleaving parity bits into user bits to guarantee run-length constraint A method of satisfying a specified run length constraint is disclosed. A systematically error correction encoded sequence of received symbols is received,... |
| US-8,161,346 |
Data refresh apparatus and data refresh method According to one embodiment, a data refresh apparatus which refreshes data stored in a storage device having storage areas, comprises an error detector... |
| US-8,161,345 |
LDPC decoders using fixed and adjustable permutators In one embodiment, the present invention is a low-density parity-check (LDPC) decoder that has a plurality of variable node units (VNUs) that generate variable... |
| US-8,161,344 |
Circuits and methods for error coding data blocks A description is given of a circuit for creating an error coding data block for a first data block, including a first error coding path adapted to create the... |
| US-8,161,343 |
Nibble encoding for improved reliability of non-volatile memory A wireless device to include a non-volatile memory to execute an encoding scheme to provide single-cell error detection and correction on program operations in... |
| US-8,161,342 |
Forward and reverse shifting selective HARQ combining scheme for OFDMA
systems A method and apparatus for combining retransmitted hybrid automatic repeat-request (HARQ) messages at different stages in an OFDM/OFDMA receiver are provided. A... |
| US-8,161,341 |
Method of transmitting control information in wireless communication
system and transmission window updating... A method of transmitting control information in a wireless communication system and transmission window updating method using the same are disclosed, by which... |
| US-8,161,340 |
Apparatus and method for recording and/or reproducing data on an
information storage medium using padding... An apparatus and method for recording and/or reproducing data on a disc are provided using padding information, and a corresponding information storage medium.... |
| US-8,161,339 |
Content playback apparatus, content playback method, and storage medium When a content playback apparatus has detected a content data acquisition error in a process of acquiring title screen content serving as next content that is... |
| US-8,161,338 |
Modular compaction of test responses Exemplary embodiments of a compactor for compacting test responses are disclosed. In certain embodiments, the compactor comprises circular registers and has... |
| US-8,161,337 |
Serially connected circuit blocks with TAPs and wrapper enable lead In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture,... |
| US-8,161,336 |
Apparatus and method for testing and debugging an integrated circuit A system receives serial messages from a device under test. The system includes a deserializer configured to i) receive the serial messages and, ii) based on... |
| US-8,161,335 |
System and method for testing a circuit A system for testing a circuit. The system comprises a first circuit mounted on an embedded first circuit board and a test circuit mounted on the embedded first... |
| US-8,161,334 |
Externally maintained remap information Disclosed is a system comprising a memory device, a controller to maintain remap information regarding the memory device, and a storage unit to store the... |
| US-8,161,333 |
Information processing system An information processing system includes a dynamic random access memory, a processor for information processing in cooperation with the dynamic access memory,... |
| US-8,161,332 |
Pluggable transceiver module with enhanced circuitry Pluggable transceiver modules with additional functions and circuitry contained within the module. In a first embodiment, additional circuitry is added to... |
| US-8,161,331 |
Data training system and method thereof A data training system and method thereof are provided. The example data training system may include a memory controller transmitting a given data pattern to a... |
| US-8,161,330 |
Self-service terminal remote diagnostics A method for determining for determining a root cause of each of a plurality of operational faults is provided. The method includes receiving electronic... |
| US-8,161,329 |
Generating random sequences based on stochastic generative model having
multiple random variates Random sequences are generated based on a stochastic generative model having multiple random variates. Inputs representative of the stochastic generative model... |
| US-8,161,328 |
Debugger interface A system is disclosed comprising a processor, and a debug circuit. The debug circuit comprises a reset circuit configured to detect when the system is released... |
| US-8,161,327 |
Process and system for the verification of correct functioning of an
on-chip memory A method is for making an integrated circuit with built-in self-test. The method includes forming at least one nonvolatile read only memory (ROM) to store ROM... |
| US-8,161,326 |
Method and system for managing information technology (IT) infrastructural
elements The present invention provides a method, system and computer program product for managing the Information Technology (IT) infrastructural elements of multiple... |
| US-8,161,325 |
Recommendation of relevant information to support problem diagnosis The disclosure generally relates to knowledge retrieval using a knowledgebase storing general and/or expert knowledge. In particular, the disclosure relates to... |
| US-8,161,324 |
Analysis result stored on a field replaceable unit A system and method for recording fault information in an electronic system are disclosed herein. A system includes fault analysis logic and a plurality of... |
| US-8,161,323 |
Health monitor Techniques for proactively and reactively running diagnostic functions. These diagnostic functions help to improve diagnostics of conditions detected in a... |
| US-8,161,322 |
Methods and apparatus to initiate a BIOS recovery Methods and apparatus to initiate a basic input/output system (BIOS) recovery are disclosed herein. An example BIOS recovery module includes a memory storing... |
| US-8,161,321 |
Virtual machine-based on-demand parallel disaster recovery system and the
method thereof Embodiments disclosed herein related to a virtual machine-based on-demand parallel disaster recovery system and a method thereof. By integrating context of... |
| US-8,161,320 |
Apparatus, memory device controller and method of controlling a memory
device An apparatus, memory device controller and method of controlling a memory device are provided. The example apparatus may include a bad block bitmap referencing... |
| US-8,161,319 |
Integrating content-laden storage media with storage system Integrating content into a storage system with substantially immediate access to that content. Providing high reliability and relatively easy operation with a... |
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