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Patent # Description
US-8,161,267 Methods and apparatus for scalable array processor interrupt detection and response
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these...
US-8,161,266 Replicating opcode to other lanes and modifying argument register to others in vector portion for parallel...
An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode,...
US-8,161,265 Techniques for multi-level indirect data prefetching
A technique for performing data prefetching using multi-level indirect data prefetching includes determining a first memory address of a pointer associated with...
US-8,161,264 Techniques for data prefetching using indirect addressing with offset
A technique for performing data prefetching using indirect addressing includes determining a first memory address of a pointer associated with a data prefetch...
US-8,161,263 Techniques for indirect data prefetching
A processor includes a first address translation engine, a second address translation engine, and a prefetch engine. The first address translation engine is...
US-8,161,262 Storage area dynamic assignment method
A storage system allocates a data storage area in response to an access request from a first computer if the capacity of a first physical storage device...
US-8,161,261 Method and apparatus for operating data, such as totaling data, etc
A totaling device includes a first specification unit comprising a first storage unit for storing first dividing information and first interpolation value...
US-8,161,260 Optimal memory allocation for guested virtual machine(s)
Methods and apparatus allocate and adjust memory of a hardware platform hosting a plurality of guest virtual machines. One of the virtual machines is configured...
US-8,161,259 Computer system, storage system and method for saving storage area by integrating same data
Provided is a storage system capable of saving actually used physical storage areas and of achieving a high speed in write processing. There is disclosed a...
US-8,161,258 Method to qualify access to a block storage device via augmentation of the device'S controller and firmware flow
A method to qualify access to a block storage device via augmentation of the device's controller and firmware flow. The method employs one or more block...
US-8,161,257 Remote copy system
Provided is a remote copy system capable of guaranteeing the time ordering of data to be handled by a remote site even when the tasks at the remote site are...
US-8,161,256 Remote copy system and path setting support method
A remote copy system includes: a host computer; a first storage system connected to the host computer; and a second storage apparatus connected to the first...
US-8,161,255 Optimized simultaneous storing of data into deduplicated and non-deduplicated storage pools
One aspect of the present invention includes an optimized simultaneous storage operation for data objects onto a combination of deduplicated and ...
US-8,161,254 Method for creating consistent backup image of a storage volume without requiring a snapshot
Method for creating a consistent image, on a destination volume, of a target volume that remains in production use while the image is being created, without...
US-8,161,253 Maintenance of valid volume table of contents
A method maintains a valid volume table of contents (VTOC) written to in a fast replication relationship. A fast replication query is issued to a track in which...
US-8,161,252 Memory interface with dynamic selection among mirrored storage locations
Devices and methods provide data from multiple storage locations to a processor. A data block containing data required by a processor is stored in two or more...
US-8,161,251 Heterogeneous storage array optimization through eviction
A storage system can comprise storage devices having storage media with differing characteristics. An eviction handler can receive information regarding the...
US-8,161,250 Methods and systems for partially-transacted data concurrency
Aspects of the present invention comprise systems and methods for protecting multi-threaded access to shared memory. Some aspects provide higher data...
US-8,161,249 Method and apparatus for multi-port arbitration using multiple time slots
An apparatus includes a programmable device that has an interface and command ports that can each receive commands, each command requesting an information...
US-8,161,248 Simplifying and speeding the management of intra-node cache coherence
A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present...
US-8,161,247 Wait loss synchronization
Synchronizing threads on loss of memory access monitoring. Using a processor level instruction included as part of an instruction set architecture for a...
US-8,161,246 Prefetching of next physically sequential cache line after cache line that includes loaded page table entry
A microprocessor includes a cache memory, a load unit, and a prefetch unit, coupled to the load unit. The load unit is configured to receive a load request that...
US-8,161,245 Method and apparatus for performing data prefetch in a multiprocessor system
A method and apparatus for performing data prefetch in a multiprocessor system are disclosed. The multiprocessor system includes multiple processors, each...
US-8,161,244 Multiple cache directories
A first portion of an identifier can be used to assign the identifier to a slot in a first directory. The identifier can identify a cache unit in a cache. It...
US-8,161,243 Address translation caching and I/O cache performance improvement in virtualized environments
Methods and apparatus relating to improving address translation caching and/or input/output (I/O) cache performance in virtualized environments are described....
US-8,161,242 Adaptive spill-receive mechanism for lateral caches
Improving cache performance in a data processing system is provided. A cache controller monitors a counter associated with a cache. The cache controller...
US-8,161,241 Temperature-aware buffered caching for solid state storage
A system and method for managing a cache includes monitoring a temperature of regions on a secondary storage based on a cumulative cost to access pages from...
US-8,161,240 Cache management
Systems, methods and computer readable media for cache management. Cache management can operate to organize pages into files and score the respective files...
US-8,161,239 Optimized computer system providing functions of a virtual storage system
A virtual storage system is equipped with a plurality of storage systems and a virtualization device for virtualizing the plurality of storage systems logically...
US-8,161,238 Systems and methods for avoiding performance degradation due to disk fragmentation in a network caching device
Storage space on one or more hard disks of a network caching appliance is divided into a plurality S of stripes. Each stripe is a physically contiguous section...
US-8,161,237 Asymmetric load balancing for RAID storage systems
The instant invention broadly contemplates balancing of asymmetric RAID arrays based on application usage patterns. The instantly claimed invention broadly...
US-8,161,236 Persistent reply cache integrated with file system
A system and method integrates a persistent reply cache with operation of a file system executing on a storage system. In an illustrative embodiment, the...
US-8,161,235 Storage system and data erasing method
This storage system includes a server management unit for managing in a server a maximum overwrite count and an overwrite count for overwriting the overwrite...
US-8,161,234 Dynamically switching command types to a mass storage drive
A method, device, and system are disclosed. In one embodiment method begins by receiving a first new mass storage disk access request. The method then...
US-8,161,233 Multi-stream restore system and method
A computer system and process restores files on multiple disk drives from a plurality of backup files on a plurality of media types and at a plurality of...
US-8,161,232 Periodically and empirically determined memory refresh intervals
Embodiments include a system, a memory controller, an apparatus, a device, and a method. An embodiment provides a device that includes a memory that requires a...
US-8,161,231 Device identifiers for nonvolatile memory modules
A memory card has a data scrambler that performs a data scrambling operation on data stored in the memory card according to a device ID associated with the...
US-8,161,230 Nonvolatile memory system, and data read/write method for nonvolatile memory system
A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write...
US-8,161,229 Flash memory architecture with separate storage of overhead and user data
A memory device has a plurality of dedicated data blocks for storing only user data and a plurality of dedicated overhead blocks for storing only overhead data....
US-8,161,228 Apparatus and method for optimized NAND flash memory management for devices with limited resources
An apparatus and method for managing memory in low-end electronic devices is provided. The apparatus includes a memory management unit. The memory management...
US-8,161,227 Storage subsystem capable of programming field-programmable devices of a target computer system
A non-volatile storage subsystem is capable of serving as a configuration controller for configuring/programming one or more field-programmable devices, such as...
US-8,161,226 Methods and apparatus to share a thread to reclaim memory space in a non-volatile memory file system
Example methods and apparatus to share a thread to reclaim memory space in non-volatile memory file systems are disclosed. A disclosed example method includes...
US-8,161,225 Semiconductor memory card, access device and method
A card information-storing portion is provided in a semiconductor memory card, and information relating to access performance such as access condition and...
US-8,161,224 Interface between a twin-wire bus and a single-wire bus
A method and a device for converting a first bus including at least a data wire and a clock wire into a single-wire bus, wherein a data bit of the first bus is...
US-8,161,223 Method and system for a storage device
Systems and methods for storage devices are presented. More specifically, in one embodiment a storage device may comprise have an enclosure comprising an...
US-8,161,222 Method and system and apparatus for use in data storage
Systems, devices and methods for interfacing a single bus with multiple buses invisibly to devices using the single bus are presented. More specifically, in one...
US-8,161,221 Storage system provided with function for detecting write completion
It is an object to prevent a processing speed of the storage system provided with a function for detecting a write completion of data from being reduced. A...
US-8,161,220 Method and apparatus for enhancing universal serial bus applications
A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream...
US-8,161,219 Distributed command and address bus architecture for a memory module having portions of bus lines separately...
Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of...
US-8,161,218 Network adapter, method, and computer program product
A network adapter for plugging into a host computer is provided. The network adapter may include an internal memory and connection means for connecting the host...
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