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Patent # Description
US-9,312,876 Asynchronous low-power analog-to-digital converter circuit with configurable thresholds
An analog-to-digital converter circuit is described that includes register space to keep one or more values to establish upper and lower thresholds of the...
US-9,312,875 Signal processing apparatus and method for processing a signal
A signal processing apparatus is described comprising a sampling time control circuit configured to provide a sequence of digital values, each digital value...
US-9,312,874 Analog to digital conversion (ADC)/digital to analog conversion (DAC) compression
In an embodiment, a system includes an ADC and a compression circuit associated with the ADC. The ADC may be configured to generate samples of an analog signal....
US-9,312,873 Analog-to-digital converter and image sensor
An analog-to-digital converter has a sampler to hold a sampled signal, an input signal predictor to generate a prediction signal at predetermined timing before...
US-9,312,872 Signal converter
A signal converter may include: a clock generation unit suitable for generating a counting clock signal having a given period value; a signal dividing unit...
US-9,312,871 Gas cell, quantum interference device, atomic oscillator, electronic device, and moving object
A gas cell includes an internal space in which metal atoms and a buffer gas are sealed. The buffer gas includes a gas mixture including nitrogen gas and argon...
US-9,312,870 Quantum interference device, atomic oscillator, electronic apparatus, and moving object
An atomic oscillator includes a gas cell in which metal atoms are sealed, a heating unit that is driven by the supply of power and heats the gas cell, a power...
US-9,312,869 Systems and methods for a wafer scale atomic clock
Systems and methods for a wafer scale atomic clock are provided. In at least one embodiment, a wafer scale device comprises a first substrate; a cell layer...
US-9,312,868 Clock phase adjusting circuit and semiconductor device including the same
A semiconductor device includes a buffer suitable for receiving an input signal, a clock buffer suitable for receiving a clock, a delay locked loop (DLL)...
US-9,312,867 Phase lock loop device with correcting function of loop bandwidth and method thereof
A phase lock loop (PLL) device with correcting function of loop bandwidth and method thereof is related to the method including generating an output signal by a...
US-9,312,866 Phase lock loop (PLL/FLL) clock signal generation with frequency scaling to power supply voltage
A clock signal generation circuit provides an output clock signal to a digital system. The digital system is powered by a power supply voltage, VDD, that may...
US-9,312,865 Bimodal serial link CDR architecture
A system for generating a local clock, configurable to utilize a forwarded clock and a data stream, or a data stream only, as frequency and phase references. In...
US-9,312,864 AFLL with increased timing margin
In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that...
US-9,312,863 Wave clocking
Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing...
US-9,312,862 Adaptive clocking scheme to accommodate supply voltage transients
Adaptive clocking schemes for synchronized on-chip functional blocks are provided. The clocking schemes enable synchronous clocking which can be adapted...
US-9,312,861 Protecting data from decryption from power signature analysis in secure applications
Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input...
US-9,312,860 Gated differential logic circuit
A gated differential logic circuit can include a header device having a first terminal coupled to a supply voltage, and a second terminal; a second header...
US-9,312,859 Switching circuit and method
A switching circuit that switches voltage at an output node includes a first switch element configured to enable supplying a first voltage from a first supply...
US-9,312,858 Level shifter for a time-varying input
A level shifter circuit for coupling a first circuit, that uses a first supply voltage, with a second circuit, that uses a second supply voltage, includes an...
US-9,312,857 Semiconductor circuit
A semiconductor circuit includes: a first circuit configured to provide first voltage to an output node when a voltage level of an input node is at a first...
US-9,312,856 Scheme for 3D voltage type TSV signal transmission
A method for 3D voltage type TSV signal transmission, comprising transmitting a full swing signal of data with a first voltage through TSVs for each one of a...
US-9,312,855 Touch sensor tracks
In one embodiment, a method includes receiving a touch sensor substrate associated with a plurality of electrodes and a plurality of connection pads. The...
US-9,312,854 Circuit for switching-on and/or switching-off an electrical load
A circuit for switching-on and/or switching-off an electrical load comprises an electrically conductive operator control element, an electrically operated...
US-9,312,853 High frequency semiconductor switch circuit and high frequency radio system including same
A path switching FET and a shunt FET are separated from each other by a capacitor. The gates of the path switching FET and the shunt FET are controlled using an...
US-9,312,852 Inductive load driver slew rate controller
A circuit and method for digital controlling the slew rate of load voltage are provided. The circuit is comprised of a digital slew-rate control unit that...
US-9,312,851 Semiconductor device and driving method thereof
A novel semiconductor device and a driving method thereof are provided. In the semiconductor device, a (volatile) node which holds data that is rewritten by...
US-9,312,850 Testable power-on-reset circuit
An integrated circuit with a testable power-on-reset (POR) circuit includes a voltage divider, an inverter, a level-shifter, a buffer and a flip-flop. The...
US-9,312,849 Analog signal soft switching control with precise current steering generator
A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing...
US-9,312,848 Glitch suppression in an amplifier
A driver circuit includes detectors responsive to the operating region that a driven switch is operating in. The driver circuit is operative to drive the gate...
US-9,312,847 High voltage switch
A high-voltage switching device is formed by: connecting a number of normally-on transistors, such as JFETs, in series with each other, where the drain of each...
US-9,312,846 Driver circuit for signal transmission and control method of driver circuit
A driver circuit for receiving a data input and generating an output signal according to at least the data input is provided. The driver circuit includes a pair...
US-9,312,845 Semiconductor device
In aspects of the invention, a semiconductor device can include one level shift circuit that outputs a low-side input signal as a high-side signal upon raising...
US-9,312,844 Slope compensation module
A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. The slope control unit comprises a capacitor...
US-9,312,843 Comparison circuit and impedance calibration circuit using the same
A comparison circuit includes: an offset removal unit configured to store offset information of a comparator in response to a reference voltage, and compare a...
US-9,312,842 Cascoded comparator with dynamic biasing for column parallel single slope ADCs
Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing...
US-9,312,841 Cascoded comparator with dynamic biasing for column parallel single slope ADCs
Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing...
US-9,312,840 LC lattice delay line for high-speed ADC applications
This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC)...
US-9,312,839 Buffer circuit and semiconductor integrated circuit
A buffer circuit section receives an input clock, and outputs an output clock by wave-shaping the input clock, a measurement circuit section measures a first...
US-9,312,838 Apparatus and method for transferring multiple asynchronous clock signals over a single conductor
Methods and systems for transferring two clock signals over a single conductor are disclosed. According to various disclosed embodiments, first and second input...
US-9,312,837 Dynamic margin tuning for controlling custom circuits and memories
Embodiments of a method that may allow for selectively tuning a delay of individual logic paths within a custom circuit or memory are disclosed. Circuitry may...
US-9,312,836 Reduced pin full feature load switch
A four pin integrated circuit MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) load switch is disclosed that provides full features including...
US-9,312,835 Load switch controller with slew rate control
A power control device can generate control signals to control operation of power sources. Additional control signals control operation of load switches that...
US-9,312,834 Low leakage flip-flop circuit
An integrated circuit having reduced power consumption includes a clock-gating cell, a transistor and a flip-flop. The clock-gating cell receives a dynamic...
US-9,312,833 Wireless circuit, and method for controlling wireless circuit
According to a wireless circuit, in a case where a control section carries out switching between use frequency bands of an antenna, the control section sets, in...
US-9,312,832 High power filter with single adjust for multiple channels
A RF filter system for filtering radio frequency is provided. A first plurality of capacitors, said first plurality of capacitors comprising at least a first...
US-9,312,831 Charge sharing analog computation circuitry and applications
In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of...
US-9,312,830 Volume curve adjustment for signal processing headroom
An attenuation control before digital signal processing provides digital headroom. A pre-digital signal processing volume control receives a volume control...
US-9,312,829 System for adjusting loudness of audio signals in real time
A method of adjusting a loudness of an audio signal in real time may include receiving an electronic audio signal and dividing the audio signal into a plurality...
US-9,312,828 Method and circuit for controlled gain reduction of a differential pair
The present document relates to multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to...
US-9,312,827 Network enabled audio device and radio site
A device for receiving an Internet radio broadcast is provided. The device comprises a communication interface, at least one input control mounted on the...
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