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Merged fin structures for finFET devices
Merged fin structures for finFET devices and methods of manufacture are disclosed. The method of forming the structure includes forming a plurality of fin...
Structure and method to reduce crystal defects in epitaxial fin merge
using nitride deposition
FinFET devices and methods of making the same. A structure includes: a substrate with a buried insulator, a plurality of fins over the buried insulator, and a...
Implementing buried FET utilizing drain of finFET as gate of buried FET
A method and circuit for implementing an enhanced transistor topology with a buried field effect transistor (FET) utilizing the drain of a FinFET as the gate of...
Non-volatile memory device and method for manufacturing same
According to an embodiment, a non-volatile memory device includes electrodes, an inter-layer insulating film between the electrodes and at least one...
Methods of manufacturing three-dimensional semiconductor memory devices
Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second...
A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In...
Integrated circuits with FinFET nonvolatile memory
Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a first and second fin...
In a memory cell array region and a source contact region defined in a surface of a semiconductor substrate, a memory cell transistor including a floating gate...
Memories with memory arrays extending in opposite directions from a
semiconductor and their formation
Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a...
Apparatus for high speed ROM cells
A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a second first-level contact formed on a...
Non-volatile memory device
The present invention provides a non-volatile memory device using a memory transistor including an oxide semiconductor, capable of writing with low power...
Static random access memory cell and forming method thereof
A SRAM cell and a forming method thereof are provided. The SRAM cell includes: a pull-up transistor, a pull-down transistor, a pass gate transistor, a tensile...
Dynamic random access memory unit and fabrication method thereof
A dynamic random access memory unit includes a substrate having a trench disposed therein, a self-aligned trench isolation structure formed in the bottom...
A semiconductor device includes first and second well regions having a first conductivity type, and a third well region between the first and second well...
Integrated circuits and manufacturing methods thereof
An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source...
Integrated circuit structure with thinned contact
Embodiments of mechanism for an integrated circuit (IC) structure are provided. The IC structure includes a substrate including a first diffusion region, a...
Strained silicon structure
A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate...
A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are...
Bidirectional silicon carbide transient voltage supression devices
An electronic device includes a silicon carbide layer having a first conductivity type and having a first surface and a second surface opposite the first...
Method and apparatus for electrostatic discharge protection
This application discusses, among other things, apparatus and methods for electrostatic discharge (ESD) protection. In an example, an ESD protection circuit can...
Semiconductor multi-project or multi-product wafer process
The embodiment provides a semiconductor MP wafer process including processing a plurality of MP wafers in a lot or batch with a first process step. The...
Heterogeneous integration of memory and split-architecture processor
A method for fabricating a semiconductor device provides a first chip having first terminals, a second chip having second terminals, and a third chip having...
Method of manufacturing a semiconductor device having a chip mounted on an
A semiconductor device 100 includes: a first semiconductor package 10; a first interposer 12 having an upper surface on which the first semiconductor package 10...
Display panel and manufacturing method thereof
A display panel including an array substrate and a COF substrate is provided. The COF is provided with a plurality of welded lead lines. The array substrate...
Chip, chip arrangement and method for producing a chip
Various embodiments provide a chip. The chip has a carrier, an integrated circuit formed above the carrier, and an energy storage element. The energy storage...
Semiconductor light emitting device
In a semiconductor light emitting device, a light emitting structure includes a first-conductivity type semiconductor layer, an active layer, and a...
Light-emitting diode lighting device
A light-emitting diode (LED) lighting device includes a substrate, a first bottom electrode, a bottom transparent isolation layer, a first vertical LED, a...
Illuminating device and light module thereof
An illuminating device includes a first light module and a second light module. The first light module emits a first light beam to a first illuminating area,...
Light emitting device and lighting system having the same
The present invention provides a light emitting device comprising a first light emitting portion that emits white light at a color temperature of 6000K or more...
III-nitride device and FET in a package
One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop...
Multiple die stacking for two or more die
A microelectronic package can include a substrate having first and second opposed surfaces, and first and second microelectronic elements having front surfaces...
A semiconductor package may include a first substrate, a second substrate facing the first substrate, a plurality of first electrical connections disposed...
Dense-pitch small-pad copper wire bonded double IC chip stack packaging
piece and preparation method therefor
A dense-pitch small-pad copper wire bonded double IC chip stack package comprises a plastic package body, in which a lead frame carrier and a frame lead inner...
A semiconductor device includes an operation circuit formed on a top surface of a semiconductor substrate, a memory array formed over the operation circuit, an...
Semiconductor packages and methods of packaging semiconductor devices
A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes...
Enhanced stacked microelectronic assemblies with central contacts and
improved thermal characteristics
A microelectronic assembly includes a first unit and a second unit overlying the first unit. Each of the units include a dielectric element that includes first...
Integrated circuit package with spatially varied solder resist opening
An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed...
Semiconductor device, wireless device, and storage device
According to one embodiment, a semiconductor device includes a substrate, a first semiconductor chip, a second semiconductor chip, and a discrete element part....
Aluminum-based alloy conductive wire used in semiconductor package and
manufacturing method thereof
An aluminum-based alloy conductive wire used in semiconductor package is composed of 0.05 to 0.14 weight percent scandium (Sc), 0.01 to 0.1 weight percent...
Semiconductor module and method for manufacturing the same
There is provided a semiconductor module and a method for manufacturing the same which make it possible to joint the electrode of the bare-chip transistor and...
Method of forming molded panel embedded die structure
Methods of forming molded panel coreless package structures are described. Those methods and structures may include fabrication of embedded die packages using...
Conductive bump, semiconductor chip and stacked semiconductor package
using the same
A conductive bump includes a step member formed to form a step on a portion of a connection pad; and a conductive member formed on the connection pad and the...
Method and apparatus for high temperature semiconductor device packages
and structures using a low temperature...
A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver...
Conductive pillar structure for semiconductor substrate and method of
A conductive pillar structure for a die includes a passivation layer having a metal contact opening over a substrate. A bond pad has a first portion inside the...
Hybrid bonding with air-gap structure
A package component includes a surface dielectric layer having a first planar surface, and a metal pad in the surface dielectric layer. The metal pad includes a...
Semiconductor device and method for manufacturing semiconductor device
An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for...
Method of joining semiconductor substrate
A method of joining semiconductor substrates, which may include: forming an alignment key on a first semiconductor substrate; forming an insulating layer on the...
Semiconductor device having an identification mark
A semiconductor device includes a chip, a contact pad arranged over the front side of the chip and an identification mark arranged over the contact pad. The...
Bump structure for stacked dies
A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the...
Interconnect structure containing a porous low k interconnect
A porous low k dielectric material containing atoms of at least Si, C, N and H (C and/or O may also be present) is used to provide an interconnect structure...