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Patent # Description
US-9,312,223 Method for fabricating a carbon nanotube interconnection structure
The present invention relates to an interconnection structure and a method for fabricating the same. According to the present invention, cavities are formed...
US-9,312,222 Patterning approach for improved via landing profile
The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed...
US-9,312,221 Variable capacitance devices
A variable capacitance device includes a capacitor having a first capacitance and a variable resistor coupled in series with the capacitor. The variable...
US-9,312,220 Structure and method for a low-K dielectric with pillar-type air-gaps
A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment,...
US-9,312,219 Interposer and packaging substrate having the interposer
An interposer is provided, including a composite body and a plurality of conductive through vias penetrating the composite body. The composite body includes at...
US-9,312,218 Semiconductor device and method of forming leadframe with conductive bodies for vertical electrical...
A semiconductor device has a semiconductor die mounted to a substrate. A leadframe has a base plate and integrated tie bars and conductive bodies. The tie bars...
US-9,312,217 Methods for making a starting substrate wafer for semiconductor engineering having wafer through connections
The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It...
US-9,312,216 Semiconductor device with semiconductor chip and wiring layers
To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which...
US-9,312,215 Semiconductor memory system
According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer...
US-9,312,214 Semiconductor packages having polymer-containing substrates and methods of forming same
A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising...
US-9,312,213 Bump structures having an extension
A bump structure may include a body portion spaced apart from a pad disposed on a substrate and a first extension extending from a side of the body portion onto...
US-9,312,212 Method for housing an electronic component in a device package and an electronic component housed in the device...
A method for housing an electronic component in a device package includes providing a first substrate, wherein the electronic component is arranged in a...
US-9,312,211 Semiconductor device and manufacturing method thereof
The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device has a plurality of power units placed in...
US-9,312,210 Semiconductor device with air gap and method for fabricating the same
A method for fabricating a semiconductor device includes forming, over a substrate, a plurality of first conductive structures which are separated from one...
US-9,312,209 Semiconductor device
A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to...
US-9,312,208 Through silicon via structure
A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a...
US-9,312,207 Semiconductor device
A semiconductor device including a semiconductor substrate having a first surface and a second surface, the first surface being configured for formation of a...
US-9,312,206 Semiconductor package with thermal via and method for fabrication thereof
A semiconductor package includes a semiconductor die having an active face and dielectric layers disposed on the active face of the semiconductor die. At least...
US-9,312,205 Methods of forming a TSV wafer with improved fracture strength
A method including forming a through-substrate via through a thickness of a substrate, the thickness of the substrate is measured from a front side of the...
US-9,312,204 Methods of forming parallel wires of different metal materials through double patterning and fill techniques
An integrated circuit and a method of forming an integrated circuit including a first dielectric layer including a surface, a plurality of first trenches...
US-9,312,203 Dual damascene structure with liner
A dual damascene structure with an embedded liner and methods of manufacture are disclosed. The method includes forming a dual damascene structure in a...
US-9,312,202 Method of forming a semiconductor substrate including a cooling channel
A semiconductor substrate for use in an integrated circuit, the semiconductor substrate including a channel defined on a surface of the substrate. The channel...
US-9,312,201 Heat dissipation device
A heat dissipation device for a heat-generating component includes at least one helically-shaped air tube having a length. The at least one air tube is...
US-9,312,200 Solid structures for thermal management
Solid structures for thermal management are provided. In one aspect, the solid structures can comprise a metal-ceramic composite member assembled to be in...
US-9,312,199 Intelligent chip placement within a three-dimensional chip stack
An integrated circuit (IC) stack device for thermal management is disclosed. The IC stack device can include a primary IC having a first set of cores with a...
US-9,312,198 Chip package-in-package and method thereof
An electronic package includes an interposer, a die attached to a first side of the interposer, an embedded electronic package attached to a second side of the...
US-9,312,197 Support base-attached encapsulant, encapsulated substrate having semiconductor devices mounted thereon,...
Support base-attached encapsulant for collectively encapsulating a semiconductor device mounting surface of a substrate or semiconductor device forming surface...
US-9,312,196 Curable silicone composition, cured product thereof, and optical semiconductor
The present invention relates to a curable silicone composition comprising: (A) an organopolysiloxane having at least two alkenyl groups in a molecule and...
US-9,312,195 Semiconductor device
A first photosensitive organic insulating film (PO1) formed in contact with a passivation film (PL) covers the entire circumference of a stepped portion (TRE)...
US-9,312,194 Integrated circuit packaging system with terminals and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting platform; applying an attach layer on the...
US-9,312,193 Stress relief structures in package assemblies
A semiconductor package structure, comprises a substrate, a die region having one or more dies disposed on the substrate, and at least one stress relief...
US-9,312,192 Semiconductor device
A semiconductor device includes: a plurality of semiconductor modules, each of which includes a semiconductor circuit having a circuit board on which at least...
US-9,312,191 Block patterning process for post fin
A method of reducing etch time needed for patterning an organic planarization layer (OPL) in a block mask stack so as to minimize damages to gate structures and...
US-9,312,190 Semiconductor device and method of manufacturing the same
The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first metal gate...
US-9,312,189 Methods for fabricating integrated circuits with improved implantation processes
Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having...
US-9,312,188 Method for fabricating semiconductor device
In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and...
US-9,312,187 Semiconductor device and method of manufacturing the same
The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a...
US-9,312,186 Method of forming horizontal gate all around structure
This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the...
US-9,312,185 Formation of metal resistor and e-fuse
Embodiments of present invention provide a method of forming metal resistor. The method includes forming a first and a second structure on top of a...
US-9,312,184 Semiconductor devices and methods of manufacturing the same
In a method of manufacturing a semiconductor device, a split gate structure is formed on a cell region of a substrate including the cell region and a logic...
US-9,312,183 Methods for forming FinFETS having a capping layer for reducing punch through leakage
A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a...
US-9,312,182 Forming gate and source/drain contact openings by performing a common etch patterning process
One method disclosed herein includes forming an opening in a layer of material so as to expose the source/drain regions of a transistor and a first portion of a...
US-9,312,181 Semiconductor device, electronic device including the same and manufacturing methods thereof
The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed...
US-9,312,180 Method for forming semiconductor structure
The present invention provides a method for forming a semiconductor structure, including the following steps: Firstly, a substrate is provided, the substrate...
US-9,312,179 Method of making a finFET, and finFET formed by the method
A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between,...
US-9,312,178 Method of dicing thin semiconductor substrates
A method of dicing a plurality of integrated devices included in a semiconductor substrate using laser energy comprises the steps of directing a first laser...
US-9,312,177 Screen print mask for laser scribe and plasma etch wafer dicing process
Methods of using a screen-print mask for hybrid wafer dicing using laser scribing and plasma etch described. In an example, a method of dicing a semiconductor...
US-9,312,176 Removing conductive material to form conductive features in a substrate
Apparatuses having, and methods for forming, conductive features are described. A hole is formed in a substrate and a conductive material is deposited in the...
US-9,312,175 Surface modified TSV structure and methods thereof
Microelectronic elements and methods of their manufacture are disclosed. A microelectronic element may include a substrate including an opening extending...
US-9,312,174 Method for manufacturing contact plugs for semiconductor devices
A method for manufacturing contact plugs for semiconductor devices includes the following steps. A substrate is provided. The substrate includes a plurality of...
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