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Patent # Description
US-9,312,023 Devices and methods of programming memory cells
Devices and methods of programming memory cells, both SLC and MLC, such as to reduce charge-storage structure to charge-storage structure coupling, are shown...
US-9,312,022 Memory timing self-calibration
Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes...
US-9,312,021 Cell string and reading method for the cell string
Provided are a cell string and a reading method for the cell string. The cell string includes a semiconductor body formed on a surface of an insulating layer,...
US-9,312,020 Methods of operating memory devices
Methods of operating a memory device include applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of...
US-9,312,019 Memory device and method for operating the same
According to an embodiment, an operation method for a memory device which has a first memory element and a second memory element respectively provided on both...
US-9,312,018 Sensing with boost
The present disclosure relates to sensing with boost. An apparatus includes boost logic. Boost logic includes a boost source and a plurality of boost interfaces...
US-9,312,017 Storage in charge-trap memory structures using additional electrically-charged regions
A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to...
US-9,312,016 Multi-level cell memory device and method of operating multi-level cell memory device
A read method of a multi-level cell memory device includes receiving a first read command, and reading first and second hard decision data by performing first...
US-9,312,015 Methods for reducing body effect and increasing junction breakdown voltage
Methods for reducing an increase in the threshold voltage of a transistor due to the body effect and increasing the junction breakdown voltage for junctions of...
US-9,312,014 Single-layer gate EEPROM cell, cell array including the same, and method of operating the cell array
A cell array portion of a single-layer gate EEPROM device includes a plurality of unit cells formed over a substrate to share a first well region in the...
US-9,312,013 Configuration method of erase operation, memory controlling circuit unit and memory storage device
A configuration method of erase operation, a memory controlling circuit unit, and a memory storage device are provided. The method includes: determining whether...
US-9,312,012 EEPROM programming with first and second programming modes
A method of programming an EEPROM, including: a first mode where a writing into cells is performed under a first voltage; and a second mode where the writing is...
US-9,312,011 Data writing method, memory storage device and memory control circuit unit
A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: writing data into at least one first...
US-9,312,010 Programming of drain side word line to reduce program disturb and charge loss
Techniques are provided for programming the memory cells of a drain-side edge word line of a set of word lines before programming memory cells of any other word...
US-9,312,009 Non-volatile memory and associated memory array, row decoder, column decoder, write buffer and sensing circuit
A non-volatile memory includes a memory array, a row decoder, a column decoder, a write buffer and a sensing circuit. The column decoder includes a programming...
US-9,312,008 Nonvolatile memory device and method of operating the same
According to example embodiments, an operation method of a nonvolatile memory device includes determining a location of a selected word line among word lines...
US-9,312,007 Memory device and method having charge level assignments selected to minimize signal coupling
A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the...
US-9,312,006 Non-volatile ternary content-addressable memory with resistive memory device
A scheme for non-volatile ternary content-addressable memory with resistive memory device is proposed. The non-volatile ternary content-addressable memory...
US-9,312,005 Accessing memory cells in parallel in a cross-point array
Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first...
US-9,312,004 Driver for semiconductor memory and system including the same
A driver for a semiconductor memory may reduce an error in writing data in memory cells by adjusting the height and width of a spike current, when the memory...
US-9,312,003 Semiconductor memory device and method of performing setting operation in semiconductor memory device
A semiconductor memory device comprises: a plurality of first lines; a plurality of second lines extending to intersect the first lines; a plurality of memory...
US-9,312,002 Methods for programming ReRAM devices
A programming technique for a set of resistance-switching memory cells such as ReRAM cell involves programming the low resistance cells to the high resistance...
US-9,312,001 Writing and verifying circuit for a resistive memory and method for writing and verifying a resistive memory
A writing and verifying circuit and a method for writing and verifying a resistive memory thereof are provided. The steps of the method includes: enabling at...
US-9,312,000 Semiconductor apparatus
A semiconductor apparatus includes first and second variable resistors, a variable resistor selection unit and a threshold voltage adjustment unit. The variable...
US-9,311,999 Memory sense amplifiers and memory verification methods
Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a...
US-9,311,998 Apparatus to store data and methods to read memory cells
Apparatus to store data and methods to read memory cells are disclosed. A disclosed example method involves, during a read cycle of a memory cell, applying a...
US-9,311,997 Resistive memory device with word lines coupled to multiple sink transistors
A resistive memory device includes memory cell array blocks, a reference cell array block, two first and second sink transistors, and a word line. Each of the...
US-9,311,996 Semiconductor storage device having resistance-change storage elements
A semiconductor storage device according to an embodiment includes a plurality of resistance-change storage elements. A plurality of bit lines are connected to...
US-9,311,995 Semiconductor memory device and control method thereof
A semiconductor memory device comprises: first lines disposed in a first direction perpendicular to a substrate and extending in a second direction parallel to...
US-9,311,994 Non-volatile memory device
The invention concerns a memory device comprising: a first memory cell comprising a first resistive non-volatile data storage element programmable to store a...
US-9,311,993 Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device comprises a memory cell array including a plurality of memory cells, and a control circuit for the memory cell array....
US-9,311,992 Decoding system and method for electronic non-volatile computer storage apparatus
Methods are systems for calculating log-likelihood ratios for a decoder utilized in an electronic non-volatile computer storage apparatus are disclosed. A...
US-9,311,991 Solid state drive with hybrid storage mode
A solid state drive (SSD) with a hybrid storage mode includes a flash memory, and a data processing module in information communication with the flash memory....
US-9,311,990 Pseudo dual port memory using a dual port cell and a single port cell with associated valid data bits and...
A pseudo dual port memory includes a set of dual port memory cells having a read port and a write port, and configured to store data words in each of a...
US-9,311,989 Power gate for latch-up prevention
In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the...
US-9,311,988 Storage control system and method, and replacing system and method
A row buffer 102 in DRAM 100 stores any data read from a memory array 101 in a specified data length unit. An LLC 206 is cache memory, and extracts and stores a...
US-9,311,987 Semiconductor memory device controlling refresh cycle, memory system, and method of operating the semiconductor...
A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array...
US-9,311,986 Semiconductor memory device
A semiconductor memory device includes a control signal generator suitable for generating a control signal corresponding to temperature information, a refresh...
US-9,311,985 Memory and memory system for periodic targeted refresh
A memory includes a plurality of word lines, a target address generation unit generating one or more target addresses by using a stored address, a refresh...
US-9,311,984 Smart refresh device
A smart refresh device includes an address control block configured to determine whether a specific row address is a row hammer address, and invert a first row...
US-9,311,983 Dynamically applying refresh overcharge voltage to extend refresh cycle time
A refresh voltage control engine selectively applies different high voltages to use in refresh operations. The control engine can detect that a portion of a...
US-9,311,982 Semiconductor device, electronic component, and electronic device
A highly reliable semiconductor device. In a configuration where a precharged source line is discharged to a bit line by establishing electrical continuity...
US-9,311,981 Semiconductor memory device having variable resistance memory and operating method
A semiconductor memory device includes a memory cell array of nonvolatile memory cells having a variable resistance element, and a conductor line array capable...
US-9,311,980 Word line supply voltage generator for a memory device and method therefore
A word line supply voltage generator is selectively activated and deactivated to allow internal memory operations that are sensitive to variations on word line...
US-9,311,979 I/O pin capacitance reduction using TSVs
Methods for reducing pin capacitance and improving off-chip driver performance by using TSVs to enable usage of off-chip drivers located within selected and...
US-9,311,978 Regulated power gating for growable memory
A circuit for an integrated circuit power gating system includes a header device connected to a bank of a segmented memory array. The circuit is structured and...
US-9,311,977 Event controlled decoding circuit
A waveform generator circuit includes a memory with address locations storing output waveform defining data bits. An address counter generates an address for...
US-9,311,976 Memory module
A memory module having integrated circuit (IC) components, a termination structure, an address/control signal path, a clock signal path, multiple data signal...
US-9,311,975 Bi-synchronous electronic device and FIFO memory circuit with jump candidates and related methods
A bi-synchronous electronic device may include a FIFO memory circuit, and a first digital circuit coupled to the FIFO memory circuit and configured to operate...
US-9,311,974 Input/output strobe pulse control circuit and semiconductor memory device including the same
An input/output strobe pulse control circuit includes a control signal generator suitable for generating first to third control signals in response to a column...
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