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Patent # Description
US-9,311,271 Method and system for logging vehicle behavior
Methods and systems for logging driving information associated with a vehicle when driven are disclosed. In one aspect, a mobile telecommunications device is...
US-9,311,270 Scheduler and scheduling method for reconfigurable architecture
A scheduler and scheduling method perform scheduling for a reconfigurable architecture. The scheduling, performed by the scheduler, includes path information...
US-9,311,269 Network proxy for high-performance, low-power data center interconnect fabric
A system and method are provided for network proxying. The network proxying may occur in a node of a fabric or across nodes in the fabric. In the network...
US-9,311,268 Method and system for communication with peripheral devices
Methods and systems for ignoring protocol defined framing errors at a peripheral device coupled to a processor via an interconnect system are provided. When a...
US-9,311,266 Hidden base address register programming in peripheral component interconnect express buses
A mapping and correspondence may be established between a virtual topology and a physical topology of a PCIe subsystem, and a host may be presented with the...
US-9,311,265 Techniques for improving throughput and performance of a distributed interconnect peripheral bus connected to a...
A method for accelerating execution of read operations in a distributed interconnect peripheral bus, the distributed interconnect peripheral bus is coupled to a...
US-9,311,264 Pass-through converged network adaptor (CNA) using existing Ethernet switching device
According to one embodiment, a switch system includes an external host connected via a peripheral component interconnect express (PCIe) port to a switch system,...
US-9,311,263 Input/output switching module interface identification in a multi-server chassis
An interface identification system includes an IHS enclosure including a plurality of IHS slots and a plurality of input/output (I/O) switching module slots. A...
US-9,311,262 Transmission control device, memory control device, and PLC including the transmission control device
A transmission control device in the present invention includes: a data storage memory in which data are written; a plurality of data copy memories into which...
US-9,311,261 Universal serial interface and semiconductor device including the same
A universal serial interface (USI) includes two transceivers configured to separately support a plurality of serial communication standards; a buffer configured...
US-9,311,260 Context preservation during thread level speculative execution
A microarchitecture can be configured to allow a thread's speculative state to be stored when the thread is preempted. The stored speculative state can then be...
US-9,311,259 Program event recording within a transactional environment
A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the...
US-9,311,258 Method, apparatus and cable for enabling two types of HDMI communication
An electronic apparatus includes a first communication unit configured to perform I2C bidirectional communication with an external apparatus using two signal...
US-9,311,257 Semiconductor memory device, memory system and method of operating the same
A memory system including a plurality of memory chips is provided. The memory system includes a first memory chip and a second memory chip that share a data bus...
US-9,311,256 Storage device
A storage device includes a non-volatile memory having a plurality of storage areas. Received data is encrypted with a first cryptographic key and stored in one...
US-9,311,255 Multi-layer content protecting microcontroller
The present invention relates to a microcontroller designed for protection of intellectual digital content. The microcontroller includes a secure CPU, a...
US-9,311,254 Method and apparatus for an improved access system
A method and apparatus to enable a user to send an action message including secure credential is described. The system comprises a receiving logic to receive...
US-9,311,253 Thinly provisioned flash cache with shared storage pool
For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and...
US-9,311,252 Hierarchical storage for LSM-based NoSQL stores
Logically arranged hierarchy or tiered storage may comprise a layer of storage being a faster access storage (e.g. solid state drive (SSD)) and another (e.g.,...
US-9,311,251 System cache with sticky allocation
Methods and apparatuses for implementing a system cache within a memory controller. Multiple requesting agents may allocate cache lines in the system cache, and...
US-9,311,250 Techniques for memory de-duplication in a virtual system
Techniques for memory de-duplication in a virtual system are described. An apparatus may comprise a first processor circuit coupled to a second processor...
US-9,311,249 Managing translation of a same address across multiple contexts using a same entry in a translation lookaside...
In response to a current context, with a particular process currently in control of a processor requesting access to a shared address space, a translation...
US-9,311,248 Methods and apparatuses for monitoring activities of virtual machines
Embodiments of a method and apparatus for monitoring activity on a virtual machine are generally described herein. The activity may be monitored by a first...
US-9,311,247 Method and apparatus for detecting patterns of memory accesses in a computing system with out-of-order program...
A method for detecting patterns of memory accesses in a computing system with out-of-order program execution is provided. The method comprises identifying a...
US-9,311,246 Cache memory system
Systems and methods are disclosed that comprise a cache memory for storing a copy of a portion of data stored in a system memory and a cache load circuit...
US-9,311,245 Dynamic cache sharing based on power state
In one embodiment, the present invention includes a cache, compute engines connected to the cache, and a way mask disposed between the cache and the compute...
US-9,311,244 Enforcing ordering of snoop transactions in an interconnect for an integrated circuit
An interconnect has transaction tracking circuitry for enforcing ordering of a set of data access transactions so that they are issued to slave devices in an...
US-9,311,243 Emulated message signaled interrupts in multiprocessor systems
A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache...
US-9,311,242 Systems and methods for enabling write-back-cache aware snapshot creation
A computer-implemented method for enabling write-back-cache aware snapshot creation may include (1) identifying a cache that implements write-back caching to...
US-9,311,241 Method and apparatus to write modified cache data to a backing store while retaining write permissions
A method is described that includes performing the following for a transactional operation in response to a request from a processing unit that is directed to a...
US-9,311,240 Location and relocation of data within a cache
In one embodiment, a computer system includes a cache having one or more memories and a metadata service. The metadata service is able to receive requests for...
US-9,311,239 Power efficient level one data cache access with pre-validated tags
A system and method to implement a tag structure for a cache memory that includes a multi-way, set-associative translation lookaside buffer. The tag structure...
US-9,311,238 Demote instruction for relinquishing cache line ownership
A computer system microprocessor core having a cache subsystem executes a demote instruction to cause an exclusively owned demote instruction specified cache...
US-9,311,237 System and method of secure garbage collection on a mobile device
A method and system for performing garbage collection involving sensitive information on a mobile device. Secure information is received at a mobile device over...
US-9,311,236 Out-of-memory avoidance in dynamic virtual machine memory adjustment
An unused free memory shortage relative to an adjusted heap maximum size associated with a memory heap of application memory is detected. The adjusted heap...
US-9,311,235 Method of erasing information stored in a nonvolatile rewritable memory, storage medium and motor vehicle computer
Method of erasing information stored in a nonvolatile rewritable memory of a computer, wherein a master module sends erasing requests to a slave module of the...
US-9,311,234 Method for reliably addressing a large flash memory and flash memory
A flash memory for a host system has a multiplicity of memory blocks. The memory blocks are subdivided into memory pages which can be written to and each memory...
US-9,311,233 Load-through fault mechanism
A mechanism is provided for accessing data in a hybrid hardware managed cache in front of flash memory enabling load/store byte addressability to flash memory....
US-9,311,232 Management of memory array with magnetic random access memory (MRAM)
An embodiment of the invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash...
US-9,311,231 Connecting interface unit and memory storage device
A connecting interface unit and a memory storage device without a crystal oscillator are provided and include a frequency detector, a phase detector, an...
US-9,311,230 Local direct storage class memory access
A queued, byte addressed system and method for accessing flash memory and other non-volatile storage class memory, and potentially other types of non-volatile...
US-9,311,229 System and method for managing flash memory
A system and method for flash memory management is provided. In particular, the system and methods herein provide for management of flash memory, particularly...
US-9,311,228 Power reduction in server memory system
A system and method for reducing power consumption of memory chips outside of a host processor device inoperative communication with the memory chips via a...
US-9,311,227 Memory management
Methods and devices are provided for memory management. One embodiment includes creating a memory control block including a number of sub-blocks, where the...
US-9,311,226 Managing operational state data of a memory module using host memory in association with state change
The specification and drawings present a new apparatus and method for managing/configuring by the memory module controller storing operational state data for...
US-9,311,225 DMA channels
Communicating between an application and a hardware device. A method includes an application writing data to host physical memory using an application view of...
US-9,311,224 Manipulating a test based on a subset of similar divergent routes from different organizations
System, method, and non-transitory medium for utilizing routes followed by runs of test scenarios to manipulate a test scenario template. Runs of test scenarios...
US-9,311,223 Prioritizing test cases using multiple variables
A computer identifies lines of code of a product program that have been modified after an initial test of the product program. The computer determines the...
US-9,311,222 User interface testing abstraction
Interactions with a particular graphical user interface (GUI) of a software system are caused to be recorded and a particular one of the interactions is...
US-9,311,221 Recording program execution
Among other things, a method includes, at a computer system on which one or more computer programs are executing, receiving a specification defining types of...
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