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Patent # Description
US-9,319,076 Modulation method for improving signal conversion gain and high-gain modulator thereof
A modulation method includes sampling the first input signal by using the first local oscillation signal and the second local oscillation signal to generate the...
US-9,319,075 Wireless devices with transmission control and multiple internet protocol (IP) based paths of communication
A method and apparatus in which multiple Internet Protocol (IP) based wireless data transmissions are simultaneously provided between a wireless device and a...
US-9,319,074 Communication device, communication method, and communication program
A device receives reception packets including information packets that contains information symbols and check packets that contains check symbols and divides...
US-9,319,073 Mitigation of write errors in multi-level cell flash memory through adaptive error correction code decoding
An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory...
US-9,319,072 Parallel bit interleaver
A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword...
US-9,319,071 Parallel bit interleaver
A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and...
US-9,319,070 Method and device for decoding polar codes
Embodiments of the present invention provide a method and a device for decoding Polar codes. A reliable subset is extracted from an information bit set of the...
US-9,319,069 Reduced complexity non-binary LDPC decoding algorithm
Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective...
US-9,319,068 Apparatus and method for coding/decoding block low density parity check code in a mobile communication system
A system and method for processing a block Low Density Parity Check (LDPC) code are provided. The system includes, a decoding apparatus for decoding a block...
US-9,319,067 Storage control apparatus, storage system, and storage control method
A storage control apparatus writes n pieces of data (here, n is an integer greater than 1) in a first memory apparatus, and reads the n pieces of written data...
US-9,319,066 Parallel processing of data having data dependencies for accelerating the launch and performance of operating...
Representative embodiments are disclosed for a rapid and highly parallel decompression of compressed executable and other files, such as executable files for...
US-9,319,065 Encoding and decoding of data
An apparatus run-length encodes data to obtain a sequence of records. The data are associate to grid points of a grid and the records are defined such that they...
US-9,319,064 Method for coding a data stream
The invention relates to a method for coding a data stream (DS), wherein the data stream (DS) comprises a multiplicity of characters which are symbols (S) from...
US-9,319,063 Enhanced multi-processor waveform data exchange using compression and decompression
Configurable compression and decompression of waveform data in a multi-core processing environment improves the efficiency of data transfer between cores and...
US-9,319,062 Dynamic range reduction for analog-to-digital converters
In accordance with the exemplary embodiments of the invention there is at least an apparatus to perform a method including receiving by an analog-to-digital...
US-9,319,061 Apparatus and methods for active termination of digital-to-analog converters
Apparatus and methods for digital-to-analog conversion are disclosed. In one embodiment, an electronic system includes a bias circuit and a digital-to-analog...
US-9,319,060 Frequency response compensation in a digital to analog converter
A digital-analog converter (DAC) comprises a receiving circuit configured to receive an input bit stream and generate a first bit signal stream of the input bit...
US-9,319,059 Calibrated SAR ADC having a reduced size
The silicon real estate required for the semiconductor fabrication of a calibrated capacitor-based successive approximation register (SAR) analog-to-digital...
US-9,319,058 Interleaving error correction and adaptive sample frequency hopping for time-interleaved analog-to-digital...
Methods and apparatus for blind detection and correction of interleaving errors using all-digital processing of data output by multiple sub-ADCs of a...
US-9,319,057 Device and method for providing filtering for an analog-to-digital converter (ADC)
Devices and methods for providing filtering for an analog-to-digital converter (ADC) are described. In one embodiment, a method for providing filtering for an...
US-9,319,056 Quantum interference device, atomic oscillator, electronic apparatus, and moving object
A quantum interference device includes a gas cell into which metal atoms are sealed, a heater that heats the gas cell, a heat transmission portion that is...
US-9,319,055 Quantum interference device, atomic oscillator, electronic device, and moving object
A quantum interference device includes: a gas cell in which metal atoms are sealed; a light emitting unit which emits light to the gas cell; a light receiving...
US-9,319,054 Systems and methods utilizing randomized clock rates to reduce systematic time-stamp granularity errors in...
Systems and methods are disclosed for utilizing slave (receive) time-stamp clock rates that are different from master (sender) time-stamp clock rates to...
US-9,319,053 Phase-locked loop (PLL)
A phase-locked loop (PLL) is provided. The PLL comprises a dithering circuit that is configured to receive a second tuning signal, and dither the second tuning...
US-9,319,052 Polar receiver with reduced amplitude-phase distortion
A receiver includes a harmonic injection-locked oscillator, which receives an RF modulated signal and provides an output to two parallel signal paths. A...
US-9,319,051 Digital PLL with hybrid phase/frequency detector and digital noise cancellation
Digital phase-locked loop (PLL) with dynamic hybrid (mixed analog/digital signal) delta-sigma (.DELTA..SIGMA.) phase/frequency detector (.DELTA..SIGMA. PFD). A...
US-9,319,050 Multiple synchronizable signal generators using a single field programmable gate array
An apparatus for phase alignment of clock signals includes a sampling circuit that samples a first clock signal on edges of a reference clock signal and that...
US-9,319,049 Method and apparatus for compensating a frequency generator such as an oscillator for frequency inaccuracies
An input receives a generated frequency having a first frequency component and a second frequency component. A filter block includes filter coefficients...
US-9,319,048 Clock divider
Aspects of the disclosure provide a circuit including a logic circuit. The logic circuit is configured to operate without inputs from a first clock signal. The...
US-9,319,047 Computation of boolean formulas using sneak paths in crossbar computing
Memristor-based nano-crossbar computing is a revolutionary computing paradigm that does away with the traditional Von Neumann architectural separation of memory...
US-9,319,046 Integrated circuit capable of preventing current backflow to power line
An integrated circuit capable of preventing current backflow to a power line is provided. The integrated circuit includes an input circuit. The input circuit...
US-9,319,045 Method and apparatus for reducing gate leakage of low threshold transistors during low power mode in a...
A circuit for reducing gate leakage current in a switchable power domain of a CMOS (complementary metal oxide semiconductor) integrated circuit chip includes a...
US-9,319,044 Switch system and method for vehicle
The present invention relates to a switch system for a vehicle. The switch system, facilitates a desired switch to be accurately and conveniently manipulated in...
US-9,319,043 Generation of differential signals
The invention relates to an apparatus comprising a differential driver module configured to generate at least one differential signal having steep rise and fall...
US-9,319,042 Sensor with concurrent autosensing of output mode and manual selection
A switching sensor may automatically configure itself to a sinking or a sourcing mode by monitoring the voltage of its switched output to determine a loading...
US-9,319,041 Squelch detector
A squelch detector receives a first input signal, a second input signal VM, a first reference voltage and a second reference voltage. The first input signal and...
US-9,319,040 Distributing multiplexing logic to remove multiplexor latency on the output path for variable clock cycle,...
A controller sets a selector register of programmable delay signal logic is to a value equal to a required number of clock cycles of delay for signals output...
US-9,319,039 Forwarded clock jitter reduction
In some embodiments, a differential amplifier with duty cycle correction is provided.
US-9,319,038 Glitch free input transition detector
A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or...
US-9,319,037 Self-adjusting clock doubler and integrated circuit clock distribution system using same
In one form, a clock doubler includes a switched inverter, an exclusive logic circuit, and a control signal generation circuit. The switched inverter has first...
US-9,319,036 Gate signal adjustment circuit
A gate signal adjustment circuit for a display is disclosed. The gate signal adjustment circuit can adjust a transition time of a gate signal used to drive data...
US-9,319,035 Source synchronous bus signal alignment compensation mechanism
An apparatus having a bit lag control element that measures a propagation time beginning with assertion of a first signal and ending with assertion of a second...
US-9,319,034 Slew based process and bias monitors and related methods
An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit...
US-9,319,033 Ramp voltage generator and method for testing an analog-to-digital converter
A method and circuit for generating ramped voltages are provided. The ramp voltage generator circuit includes: a switched-capacitor amplifier having an input...
US-9,319,032 Ramp signal generating circuit and signal generator, array substrate and display apparatus
A ramp signal generating circuit and ramp signal generator, an array substrate and a display apparatus. The ramp signal generating circuit comprises a first...
US-9,319,031 High-speed CMOS ring voltage controlled oscillator with low supply sensitivity
High-speed CMOS ring voltage controlled oscillators with low supply sensitivity have been disclosed. According to one embodiment, a CML ring oscillator...
US-9,319,030 Integrated circuit failure prediction using clock duty cycle recording and analysis
A system is disclosed, which may include a clock distribution circuit. The clock distribution circuit may include a duty cycle controller to distribute a clock...
US-9,319,029 System and method for automatic filter tuning
Various methods and devices that involve tuning filters are disclosed. A disclosed method for tuning a filter comprises trimming a center frequency of the...
US-9,319,028 Signal decomposition, analysis and reconstruction using high-resolution filter banks and component tracking
A system and method for representing quasi-periodic waveforms, for example, representing a plurality of limited decompositions of the quasi-periodic waveform....
US-9,319,027 Injecting a tone for image rejection calibration
In an example, apparatus comprises: a low noise amplifier (LNA) including a first transconductor having an input to receive a differential input radio frequency...
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