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Patent # Description
US-9,318,623 Recessed termination structures and methods of fabricating electronic devices including recessed termination...
An electronic device includes a drift region, a Schottky contact on a surface of the drift region, and an edge termination structure in the drift region...
US-9,318,622 Fin-type PIN diode array
Structures and methods of manufacturing a fin-type PIN diode array include forming a plurality of first charge-type doped silicon fins disposed in parallel on a...
US-9,318,621 Rotated STI diode on FinFET technology
A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises...
US-9,318,620 Folded conical inductor
A semiconductor inductor structure may include a first spiral structure, located on a first metal layer, having a first outer-spiral electrically conductive...
US-9,318,619 Vertical gallium nitride JFET with gate and source electrodes on regrown gate
A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type...
US-9,318,618 Semiconductor device
To provide a transistor with stable electric characteristics, provide a transistor having a small current in a non-conductive state, provide a transistor having...
US-9,318,617 Method for manufacturing a semiconductor device
It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device...
US-9,318,616 Organic light emitting diode display having thin film transistor substrate using oxide semiconductor
Provided is a thin film transistor having an oxide semiconductor material for an organic light emitting diode display and a method for manufacturing the same....
US-9,318,615 Semiconductor device and method for fabricating semiconductor device
A semiconductor device according to an embodiment includes a gate electrode, a first dielectric film, an oxide semiconductor film, a second dielectric film, a...
US-9,318,614 Self-aligned metal oxide TFT with reduced number of masks and with reduced power consumption
A method of fabricating MOTFTs includes positioning opaque gate metal on a transparent substrate, depositing gate dielectric material overlying the gate metal...
US-9,318,613 Transistor having two metal oxide films and an oxide semiconductor film
An object is to stabilize electric characteristics of a semiconductor device including an oxide semiconductor to increase reliability. The semiconductor device...
US-9,318,612 Array substrate and method of fabricating the same
An array substrate includes: a substrate; a thin film transistor including a gate electrode, an oxide semiconductor layer and source and drain electrodes,...
US-9,318,611 Thin film transistor, method of manufacturing the same, and electronic apparatus
A thin film transistor includes: a gate electrode and a pair of source and drain electrodes; and a semiconductor layer having a channel formed therein, and...
US-9,318,610 Semiconductor device and method of manufacturing the same
The present invention improves the aperture ratio of a pixel of a reflection-type display device or a reflection type display device without increasing the...
US-9,318,609 Semiconductor device with epitaxial structure
A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the...
US-9,318,608 Uniform junction formation in FinFETs
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel...
US-9,318,607 Semiconductor device and method of fabricating the same
Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first source electrode configured...
US-9,318,606 FinFET device and method of fabricating same
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain...
US-9,318,605 Semiconductor device with an SGT and method for manufacturing the same
A semiconductor device includes a P.sup.+ region and an N.sup.+ region functioning as sources of SGTs and disposed in top portions of Si pillars formed on an...
US-9,318,604 Semiconductor device including a gate electrode
A semiconductor device includes a plurality of first gate electrodes buried in a semiconductor substrate including an active region and a device isolation film,...
US-9,318,603 Method of making a low-Rdson vertical power MOSFET device
The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing...
US-9,318,602 Semiconductor device and method for manufacturing semiconductor device
A semiconductor device according to one embodiment includes a semiconductor substrate, a back-gate layer formed above the semiconductor substrate, and a stacked...
US-9,318,601 Semiconductor device and method for fabricating the same
A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereover. A gate structure is disposed over the semiconductor layer,...
US-9,318,600 Silicon carbide semiconductor device and method for manufacturing same
This silicon carbide semiconductor device includes: a substrate with a principal surface; a silicon carbide layer which is arranged on a side of the principal...
US-9,318,599 Power semiconductor device
A power semiconductor device may include: a first conductive type drift layer in which trench gates are formed; a second conductive type well region formed on...
US-9,318,598 Trench MOSFET having reduced gate charge
A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the...
US-9,318,597 Layout configurations for integrating schottky contacts into a power transistor device
A semiconductor device includes a vertical field-effect-transistor (FET) and a bypass diode. The vertical FET device includes a substrate, a drift layer formed...
US-9,318,596 Ferroelectric field-effect transistor
A ferroelectric field-effect transistor device includes: a semiconductor layer; a ferroelectric layer; and an ion conductor layer arranged between the...
US-9,318,595 Method of forming gate dielectric layer and method of fabricating semiconductor device
A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide...
US-9,318,594 Semiconductor devices including implanted regions and protective layers
A semiconductor structure includes a Group III-nitride semiconductor layer, a protective layer on the semiconductor layer, a distribution of implanted dopants...
US-9,318,593 Forming enhancement mode III-nitride devices
A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on...
US-9,318,592 Active area shaping of III-nitride devices utilizing a source-side field plate and a wider drain-side field plate
In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a...
US-9,318,591 Transistor device and materials for making
This application relates to graphene based heterostructures and transistor devices comprising graphene. The hetero-structures comprise i) a first graphene...
US-9,318,590 IGBT using trench gate electrode
An IGBT includes a trench gate electrode that is bent when a semiconductor substrate is seen in a plan view, and an inner semiconductor region of the same...
US-9,318,589 Insulated gate bipolar transistor
There is provided an insulated gate bipolar transistor including: a first semiconductor area of a first conductivity type; a second semiconductor area of a...
US-9,318,588 Semiconductor device
In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second...
US-9,318,587 Injection control in semiconductor power devices
Semiconductor power devices can be formed on substrate structure having a lightly doped semiconductor substrate of a first conductivity type or a second...
US-9,318,586 High voltage semiconductor device and method for fabricating the same
According to example embodiments of inventive concepts: a semiconductor device includes: first and second trench gates extending long in one direction in a...
US-9,318,585 Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having a wide band gap...
A method of forming a semiconductor structure includes forming a first seed layer, a second seed layer and an intrinsic base spaced apart from each other and...
US-9,318,584 Isolation scheme for bipolar transistors in BiCMOS technology
Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of...
US-9,318,583 Tunnel field effect transistor and method for making thereof
A vertical tunneling field effect transistor (TFET) and method for forming a vertical tunneling field effect transistor (TFET) is disclosed. The vertical...
US-9,318,582 Method of preventing epitaxy creeping under the spacer
After forming a gate spacer on each sidewall of a sacrificial gate structure, portions of each dielectric fin cap portion underneath the gate spacer is...
US-9,318,581 Forming wrap-around silicide contact on finFET
A technique relates to a transistor. Dummy gates are formed on top of an isolation layer and over fins. Pillars are along sides of fins such that trenches...
US-9,318,580 U-shaped semiconductor structure
A method for forming a U-shaped semiconductor device includes growing a U-shaped semiconductor material along sidewalls and bottoms of trenches, which are...
US-9,318,579 Method for making a semiconductor device while avoiding nodules on a gate
A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor...
US-9,318,578 FinFET spacer formation by oriented implantation
A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed...
US-9,318,577 Semiconductor device and method for manufacturing semiconductor device
A semiconductor device is provided, which includes a single crystal semiconductor layer formed over an insulating surface and having a source region, a drain...
US-9,318,576 Method of manufacturing three-dimensional semiconductor device and variable resistive memory device
A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided. The method...
US-9,318,575 Semiconductor device and method for fabricating the same
A method of forming a semiconductor device includes forming a gate structure including a polysilicon gate and forming a capping spacer on a side surface of the...
US-9,318,574 Method and structure for enabling high aspect ratio sacrificial gates
Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles...
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