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| Patent # | Description |
|---|---|
| US-9,318,573 |
Field effect transistor having germanium nanorod and method of
manufacturing the same A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may... |
| US-9,318,572 |
Ambipolar synaptic devices Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either... |
| US-9,318,571 |
Gate structure and method for trimming spacers A gate structure includes a gate disposed on a substrate, a first spacer disposed on the substrate and surrounding the gate and a second spacer disposed on the... |
| US-9,318,570 |
Semiconductor device Provided is a semiconductor device, including a substrate including a device isolation layer and an active region isolated by the device isolation layer; a... |
| US-9,318,569 |
Unit cells of nonvolatile memory devices, cell arrays of nonvolatile
memory devices, and methods of fabricating... Unit cells including a substrate having an active region, a first charge trap pattern disposed on the substrate to intersect the active region, a second charge... |
| US-9,318,568 |
Integration of a non-volatile memory (NVM) cell and a logic transistor and
method therefor A method of making a semiconductor device includes forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the... |
| US-9,318,567 |
Fabrication method for semiconductor devices A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin... |
| US-9,318,566 |
Method of fabricating semiconductor device having grooved source contact
region In a method of fabricating a semiconductor device, a channel layer is formed on a substrate, and trench patterns are formed in the channel layer. Impurity... |
| US-9,318,565 |
Power semiconductor device with dual field plate arrangement and method of
making A semiconductor device includes a semiconductor layer, gate electrodes, an insulating film, source electrodes, and drain electrodes which are provided on the... |
| US-9,318,564 |
High density static random access memory array having advanced metal
patterning Methods and apparatus directed toward a high density static random access memory (SRAM) array having advanced metal patterning are provided. In an example,... |
| US-9,318,563 |
Silicon carbide single-crystal substrate A silicon carbide single-crystal substrate includes a first surface, a second surface opposite to the first surface, and a peripheral edge portion sandwiched... |
| US-9,318,562 |
Semiconductor apparatus with band energy alignments A semiconductor apparatus includes: a semiconductor apparatus includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer... |
| US-9,318,561 |
Device isolation for III-V substrates Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is... |
| US-9,318,560 |
Group III-V device with strain-relieving layers According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V... |
| US-9,318,559 |
Method for producing group III nitride semiconductor and template
substrate A semiconductor substrate includes a sapphire substrate including a c-plane main surface and a groove in a surface thereof, the groove including side surfaces... |
| US-9,318,558 |
MOS field effect transistor The present invention is to cause high channel mobility and a high threshold voltage to coexist in a SiC-MOSFET power device which uses a SiC substrate. The SiC... |
| US-9,318,556 |
Graphene transistor having tunable barrier Provided are graphene transistors having a tunable barrier. The graphene transistor includes a semiconductor substrate, an insulating thin film disposed on the... |
| US-9,318,555 |
Fabrication of graphene nanoelectronic devices on SOI structures A semiconductor-on-insulator structure and a method of forming the silicon-on-insulator structure including an integrated graphene layer are disclosed. In an... |
| US-9,318,554 |
Gate pad and gate feed breakdown voltage enhancement A semiconductor chip includes a semiconductor layer having first and second opposing main surfaces. A plurality of MOSFET cells are at least partially formed in... |
| US-9,318,553 |
Nanowire device with improved epitaxy As disclosed herein, a method for fabricating a nanowire device with improved epitaxy, includes forming a nanowire stack on a substrate, the nanowire stack... |
| US-9,318,552 |
Methods of forming conductive contact structures for a semiconductor
device with a larger metal silicide... One illustrative method disclosed herein includes, among other things, forming a first epi semiconductor material in a source/drain region of a transistor... |
| US-9,318,551 |
Trench isolation structures and methods for bipolar junction transistors Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a... |
| US-9,318,550 |
Semiconductor device with device separation structures A semiconductor device includes a first gate electrode structure, a second gate electrode structure, a device separation structure, and cell separation... |
| US-9,318,549 |
Semiconductor device with a super junction structure having a vertical
impurity distribution A super junction semiconductor device includes a semiconductor portion with parallel first and second surfaces. An impurity layer of a first conductivity type... |
| US-9,318,548 |
Semiconductor device A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first electrode, and a first insulating film. The semiconductor layer is... |
| US-9,318,547 |
Wide bandgap insulated gate semiconductor device A wide bandgap insulated gate semiconductor device includes a semiconductor substrate made of semiconductor having a bandgap wider than silicon; n.sup.- drift... |
| US-9,318,546 |
Doped electrode for DRAM capacitor stack In some embodiments, a metal oxide second electrode material is formed as part of a MIM DRAM capacitor stack. The second electrode material is doped with one or... |
| US-9,318,545 |
Resistor structure and method for forming the same A metal resistor structure and a method for forming the same are provided. The method includes: providing a substrate including a first and a second metallic... |
| US-9,318,544 |
Organic light emitting display apparatus, method of manufacturing the
same, and mask used in the method A method of manufacturing an organic light emitting display apparatus is provided. A plurality of first electrodes is formed on a substrate. An intermediate... |
| US-9,318,543 |
Organic light-emitting diode (OLED) display and method of manufacturing
the same An organic light-emitting diode (OLED) display and method of manufacturing the same are disclosed. In one aspect, the OLED display includes a substrate, a thin... |
| US-9,318,542 |
Method for fabricating organic light emitting diode display device with
improved effective emitting pixels area An organic light emitting diode display device includes a substrate including a display region, wherein a plurality of pixel regions are defined in the display... |
| US-9,318,541 |
Polymer film, flexible light emitting element display device, and rollable
display device The present invention relates to a polymer film containing a binder resin and polyrotaxane having a specific structure, and a flexible light emitting element... |
| US-9,318,540 |
Light emitting diode pixel unit circuit and display panel A LED pixel unit circuit and a display panel. The circuit comprises a driving module (31) which is provided with a driving control unit (311). The driving... |
| US-9,318,539 |
Organic light emitting diode display device and manufacturing method
thereof An organic light emitting diode display and a manufacturing method thereof are disclosed. The organic light emitting diode display includes: a flexible upper... |
| US-9,318,538 |
Organic light emitting diode array The disclosure relates to an organic light emitting diode array. The organic light emitting diode array includes a number of thin-film transistors arranged to... |
| US-9,318,537 |
Organic light emitting device, method of manufacturing the same, and
shadow mask therefor The present invention relates to an organic light emitting device, and the organic light emitting device according to an exemplary embodiment of the present... |
| US-9,318,536 |
Light emitters with series connection An organic solid state lighting system comprising multiple OLED modules connected in series is provided. |
| US-9,318,535 |
Vapor deposition apparatus, deposition method, and method of manufacturing
organic light-emitting display... Provided is a vapor deposition apparatus including: a plasma generator configured to change at least a portion of a first raw material gas into a radical form;... |
| US-9,318,534 |
Solid-state image pickup device and manufacturing method thereof, and
electronic apparatus Provided is a solid-state image pickup device that makes it possible to enhance image quality, and a manufacturing method thereof, and an electronic apparatus.... |
| US-9,318,533 |
Methods and systems to reduce location-based variations in switching
characteristics of 3D ReRAM arrays Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the... |
| US-9,318,532 |
Semiconductor memory device A semiconductor memory device comprises: a memory cell array comprising first wiring lines, second wiring lines extending crossing the first wiring lines, and... |
| US-9,318,531 |
SiC--Si3N4 nanolaminates as a semiconductor for MSM snapback selector
devices Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low... |
| US-9,318,530 |
Wafer level light-emitting diode array and method for manufacturing same Disclosed are a light emitting diode array on a wafer level and a method of forming the same. The light emitting diode array includes a growth substrate; a... |
| US-9,318,529 |
Wafer level light-emitting diode array A light emitting diode array is provide to include: a substrate; light emitting diodes positioned over the substrate, each including a first semiconductor... |
| US-9,318,528 |
Image sensor device and method A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is... |
| US-9,318,527 |
Method for producing photosensitive infrared detectors A method for producing at least one photosensitive infrared detector by assembling a first electronic component including plural photodiodes sensitive to... |
| US-9,318,526 |
Mechanisms for forming image-sensor device with deep-trench isolation
structure A method for fabricating an image-sensor device is provided. The method includes forming a radiation-sensing region and a doped isolation region in a... |
| US-9,318,525 |
Method for manufacturing solid-state image sensor A first pixel includes a first charge accumulation portion of a first conductivity type in a first region. A second pixel includes a second charge accumulation... |
| US-9,318,524 |
Imaging detector with per pixel analog channel well isolation with
decoupling An imaging apparatus (400) includes a detector array (412) with at least one detector tile (418). The detector tile includes a photosensor array (422) with a... |
| US-9,318,523 |
Solid-state imaging device A solid-state imaging device that includes a pixel including a photoelectric conversion section, and a conversion section that converts an electric charge... |
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