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Patent # Description
US-9,318,522 Colored radiation-sensitive composition for color filter, pattern forming method, color filter and method of...
A colored radiation-sensitive composition for a color filter that includes (A) a pigment, (B) a photopolymerization initiator, and (C) a polymerizable compound,...
US-9,318,521 Image sensor
An image sensor includes a first sub-gate in a recessed region in a substrate; a second sub-gate on the first sub-gate in contact with an upper surface of the...
US-9,318,520 Solid-state image sensing device manufacturing method and solid-state image sensing device
According to one embodiment, a solid-state image sensing device manufacturing method includes forming a photoelectric converting element, a diffusion layer...
US-9,318,519 Imaging apparatus and imaging system
One embodiment according to the present invention is an imaging apparatus including a pixel. The pixel includes first and second photoelectric conversion units,...
US-9,318,518 Photon counting detector pixel having an anode including two or more alternatively selectable and separate...
An imaging system (100) includes a radiation source (112) that emits radiation that traverses an examination region and a detector array (114) with a plurality...
US-9,318,517 Wafer level integration of focal plane arrays having a flexible conductive layer to provide an optical aperture...
Apparatus, systems, and methods related to focal plane arrays can be used in a variety of applications. In various embodiments, focal plane arrays can be...
US-9,318,516 High-frequency optoelectronic detector, system and method
An optoelectronic device for detecting electromagnetic radiation and including: a body of semiconductor material delimited by a main surface and including a...
US-9,318,515 Method of forming a conductive pattern, method of manufacturing a display substrate using the method, and...
A method of forming a conductive pattern includes forming a trench on a substrate, and providing a conductive ink to the trench while an electric field is...
US-9,318,514 Display device and method of manufacturing the same
Disclosed is a display device. The display device includes a gate line and a data line intersecting the gate line to define a pixel area on a substrate, a TFT...
US-9,318,513 Semiconductor device, active matrix board, and display device
Provided is a semiconductor device equipped with: a plurality of switching elements (T1, T2) that are connected in series; a first capacitance (Cs1) having one...
US-9,318,512 Method for manufacturing semiconductor device
As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal...
US-9,318,511 Display device having repair and detect structure comprising an isolation layer placed between the repair...
A display device having repair and detect structure includes a substrate, a pixel array, a first shorting bar and a first repair line. The pixel array disposed...
US-9,318,510 Metal wire, thin-film transistor substrate and method for manufacturing a thin-film transistor substrate
A metal wire included in a display device, the metal wire includes a first metal layer including a nickel-chromium alloy, a first transparent oxide layer...
US-9,318,509 Array substrate and method for manufacturing the same, display panel
The present invention discloses an array substrate comprising: a first substrate on which a thin film transistor and a data line are formed; and a shield metal...
US-9,318,508 Array substrate and method for producing the same, display
An array substrate, comprising: a substrate; a metal pattern formed on the substrate; an insulation layer formed on the metal pattern and formed with a via...
US-9,318,507 Thin film transistor and display device
Provided is a thin film transistor comprising an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias...
US-9,318,506 Semiconductor device and manufacturing method thereof
An object of an embodiment of the present invention is to provide a semiconductor device which includes a transistor including an oxide semiconductor with high...
US-9,318,505 Display panel and method of manufacturing the same
A display panel includes a first substrate including a switching device array, a second substrate spaced apart from the first substrate, a column spacer...
US-9,318,504 Density gradient cell array
One or more techniques or systems for mitigating density gradients between two or more regions of cells are provided herein. In some embodiments, an array of...
US-9,318,503 Nonvolatile semiconductor memory device and method for manufacturing same
A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of...
US-9,318,502 Nonvolatile memory device
A nonvolatile memory device includes a memory cell array and a peripheral circuit. The peripheral circuit is connected to the memory cell array through...
US-9,318,501 Methods and structures for split gate memory cell scaling with merged control gates
A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active...
US-9,318,500 Method of manufacturing semiconductor device
Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile...
US-9,318,499 Lithography-friendly local read circuit for NAND flash memory devices and manufacturing method thereof
A flash memory device comprising a local sensing circuitry is provided in a hierarchical structure with local and global bit lines. The local sensing circuitry...
US-9,318,498 Buried hard mask for embedded semiconductor device patterning
Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a...
US-9,318,497 Nonvolatile memory devices having single-layered floating gates
A nonvolatile memory device includes a plurality of twin cells arrayed on a substrate. Each of the plurality of twin cells includes a drain mesa protruding from...
US-9,318,496 Nonvolatile memory device with layout to minimize void formation and method of making the same
A memory device can include an array of NOR memory cells, each memory cell including a floating gate, a source on a source side of the floating gate, a drain on...
US-9,318,495 Semiconductor device including capacitor and double-layer metal contact and fabrication method thereof
Disclosed are a semiconductor device comprising a capacitor and a double-layer metal contact and a method fabricating the same. The method comprising: forming a...
US-9,318,494 Methods of forming positioned landing pads and semiconductor devices including the same
A method of forming a DRAM can include forming a plurality of transistors arranged in a first direction on a substrate and forming a bit line structure that...
US-9,318,493 Memory arrays, semiconductor constructions, and methods of forming semiconductor constructions
Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting...
US-9,318,492 Floating body storage device employing a charge storage trench
A charge storage trench structure is provided underneath a body region of a field effect transistor to store electrical charges in a region spaced from the p-n...
US-9,318,491 Semiconductor fin devices and method of fabricating the semiconductor fin devices
A semiconductor device includes a substrate, an insulating layer disposed on the substrate and having a trench exposing a surface portion of the substrate, and...
US-9,318,490 Semiconductor structure and manufacturing method thereof
The present invention provides a semiconductor structure, including a substrate, having a dielectric layer disposed thereon, a first device region and a second...
US-9,318,489 Complex circuits utilizing fin structures
A method of forming a semiconductor structure includes forming a multilayer lattice matched structure having an unstrained layer, a first strained layer, and a...
US-9,318,488 Semiconductor device and formation thereof
A semiconductor device and method of formation are provided herein. A semiconductor device includes a first active region adjacent a first side of a shallow...
US-9,318,487 High performance power cell for RF power amplifier
A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a depletion or Schottky MOSFET formed...
US-9,318,486 Semiconductor integrated circuit devices
A semiconductor integrated circuit device may include a standard cell region on a surface of a substrate and a first active region on the surface of the...
US-9,318,485 Capacitor arrangements and method for manufacturing a capacitor arrangement
In various embodiments, a capacitor arrangement is provided, which may include a substrate; a plurality of first doped regions and a plurality of second doped...
US-9,318,484 Semiconductor device
The semiconductor device of the present invention comprises first and second transistors and first and second capacitors. One of source and drain electrodes of...
US-9,318,483 Reverse blocking transistor device
A transistor device includes at least one transistor cell. The cell includes a drift region, a source region, a body region arranged between the source region...
US-9,318,482 Semiconductor devices having high-resistance region and methods of forming the same
Provided are an electrostatic discharge (ESD) protection device having a high-resistance region and a method of forming the same. The device includes a well on...
US-9,318,481 Electrostatic discharge protection device
In one aspect, a silicon-controller rectifier (SCR) includes a first N+ region; a first P+ region; a second N+ region; a second P+ region; and a P+/Intrinsic/N+...
US-9,318,480 Electrostatic discharge protection circuit
A device comprises a high voltage N well and a high voltage P well over an N+ buried layer, a high voltage P-type implanted region in the high voltage N well, a...
US-9,318,479 Electrostatic discharge (ESD) silicon controlled rectifier (SCR) with lateral gated section
In an embodiment, an ESD protection circuit may include an STI-bound SCR and a gated SCR that may be electrically in parallel with the STI-bound SCR. The gated...
US-9,318,478 Semiconductor device and fabricating method thereof
A semiconductor device includes a first dummy gate having a first width, a second dummy gate adjacent to the first dummy gate in a lengthwise direction and...
US-9,318,477 Semiconductor device having dummy cell array
A semiconductor device is disclosed. The semiconductor device includes a plurality of dummy gate lines parallel to each other in a first direction and extending...
US-9,318,476 High performance standard cell with continuous oxide definition and characterized leakage current
A transistor cell is provided that includes a dummy gate overlaying a continuous oxide definition (OD) region. A first portion of the OD region adjacent a first...
US-9,318,475 Flexible display and method of formation with sacrificial release layer
A flexible display panel and method of formation with a sacrificial release layer are described. The method of manufacturing a flexible display system includes...
US-9,318,474 Thermally enhanced wafer level fan-out POP package
In some embodiments, a semiconductor device package assembly may include a first substrate. The semiconductor device package assembly may include a first die...
US-9,318,473 Semiconductor device including a polymer disposed on a carrier
In a method of manufacturing a semiconductor device, a first semiconductor element is mounted on a carrier. A b-stage curable polymer is deposited on the...
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