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Patent # Description
US-9,318,422 Flat no-lead package and the manufacturing method thereof
A flat no-lead package includes an encapsulating material, and a die pad, a chip, a plurality of first contact pads and a plurality of second contact pads...
US-9,318,421 Power semiconductor chip with a metallic moulded body for contacting thick wires or strips and method for the...
The invention relates to a power semiconductor chip (10) having at least one upper-sided potential surface and contacting thick wires (50) or strips, comprising...
US-9,318,420 Chip stack packages, system in packages including the same, and methods of operating the same
A stack package including a first semiconductor chip and second semiconductor chip, the first semiconductor chip including first data I/O pads for transmitting...
US-9,318,419 Conductive line structures and methods of forming the same
Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating...
US-9,318,418 Semiconductor device and method of manufacturing same
In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor...
US-9,318,417 Gallium nitride devices
Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some...
US-9,318,416 Semiconductor device including conductive layer with conductive plug
Some embodiments include a semiconductor device which includes a first conductive layer formed on the semiconductor substrate and a first contact plug connected...
US-9,318,415 Beol structures incorporating active devices and mechanical strength
An integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring...
US-9,318,414 Integrated circuit structure with through-semiconductor via
The present disclosure generally provides for integrated circuit (IC) structures with through-semiconductor vias (TSV). In an embodiment, an IC structure may...
US-9,318,413 Integrated circuit structure with metal cap and methods of fabrication
The present disclosure generally provides for an integrated circuit (IC) structure with a TSV, and methods of manufacturing the IC structure and the TSV. An IC...
US-9,318,412 Method for semiconductor self-aligned patterning
A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer...
US-9,318,411 Semiconductor package with package-on-package stacking capability and method of manufacturing the same
The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred...
US-9,318,410 Cooling assembly using heatspreader
Various embodiments relate to a microchip die cooling assembly comprising a circuit board; a microchip having an exposed die attached to the circuit board; a...
US-9,318,409 Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the...
A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first...
US-9,318,408 Semiconductor device and structure
A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer...
US-9,318,407 Pop package structure
A package on package (PoP) package structure is disclosed, the structure includes at least two layers of carrier boards that are packaged and stacked in...
US-9,318,406 Device and method for determining the temperature of a heat sink
A method for determining the temperature of a heat source and an electronic unit, including a printed-circuit board equipped with a sensor and a heat sink, the...
US-9,318,405 Wafer level package without sidewall cracking
A wafer level package device may include a molding compound that encapsulates a substrate, a back end of line and front end of line layer on the substrate and a...
US-9,318,404 Semiconductor device and method of forming stress relieving vias for improved fan-out WLCSP package
A semiconductor device includes a semiconductor die. An encapsulant is disposed around the semiconductor die to form a peripheral area. An interconnect...
US-9,318,403 Integrated circuit packaging system with magnetic film and method of manufacture thereof
An integrated circuit packaging system including: connecting a first integrated circuit device and a package substrate; attaching a support bump to the package...
US-9,318,402 Resin composition, prepreg and resin sheet and metal foil-clad laminate
A resin composition is provided which can be suitably used in a printed circuit board having excellent electrical properties, heat resistance and peel strength,...
US-9,318,401 Glass composition for protecting semiconductor junction, method of manufacturing semiconductor device and...
Provided is a glass composition for protecting a semiconductor junction which contains at least SiO.sub.2, B.sub.2O.sub.3, Al.sub.2O.sub.3, ZnO and at least two...
US-9,318,400 Wafer-scale package including power source
A medical device includes a first substrate, a second substrate, a control module, and an energy storage device. The first substrate includes at least one of a...
US-9,318,399 Semiconductor wafers employing a fixed-coordinate metrology scheme and methods for fabricating integrated...
Semiconductor wafers employing a fixed coordinate metrology scheme and methods for fabricating integrated circuits using the same are disclosed. In an exemplary...
US-9,318,398 Chip-on-film package and display device having the same
A chip-on-film package includes a base film, a test line, and an integrated circuit chip. The base film includes a bent area in which a bending occurs. The test...
US-9,318,397 Stacked semiconductor chips including test circuitry
A semiconductor device includes: a first circuit block formed on a first semiconductor substrate having first and second sides extending in a first direction...
US-9,318,396 Method of fabricating flash memory
A method of fabricating a flash memory includes providing a fin structure. The fin structure includes a floating gate material, an oxide layer and a...
US-9,318,395 Systems and methods for preparation of samples for sub-surface defect review
One embodiment relates to a method of preparation of a sample of a substrate for sub-surface review using a scanning electron microscope apparatus. A defect at...
US-9,318,394 Apparatus and methods for through substrate via test
A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side...
US-9,318,393 Semiconductor device having test unit, electronic apparatus having the same, and method for testing the...
A semiconductor device can detect a defective or faulty part caused by copper (Cu) ions migrated from a through silicon via (TSV), resulting in improvement of...
US-9,318,392 Method to form SOI fins on a bulk substrate with suspended anchoring
A method of fabricating non-tilted, electrically isolated fins from a bulk substrate is provided. A plurality of semiconductor fins is formed extending upwards...
US-9,318,391 Method for manufacturing semiconductor device including a MOS-type transistor
There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high...
US-9,318,390 CMOS circuit and method for fabricating the same
A semiconductor device includes a semiconductor substrate and a gate insulation layer formed over the semiconductor substrate. A gate electrode is formed over...
US-9,318,389 Integrated circuit having plural transistors with work function metal gate structures
The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor...
US-9,318,388 Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the...
One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material...
US-9,318,387 Method for separating and transferring IC chips
A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of...
US-9,318,386 Wafer alignment methods in die sawing process
A method includes forming a molding compound molding a lower portion of an electrical connector of a wafer therein. The molding compound is at a front surface...
US-9,318,385 Systems and methods for producing flat surfaces in interconnect structures
Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an...
US-9,318,384 Dielectric liner for a self-aligned contact via structure
At least one dielectric material layer having a top surface above the topmost surface of the gate electrode of a field effect transistor is formed. Active...
US-9,318,383 Integrated cluster to enable next generation interconnect
Embodiments of the present invention generally relate to methods for forming a metal structure and passivation layers. In one embodiment, metal columns are...
US-9,318,382 Semiconductor device with air gap and method of fabricating the same
A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by...
US-9,318,381 Method of fabricating conductive line of a semiconductor device
A method of fabricating a conductive line of a semiconductor device is disclosed. The method includes the steps of: sequentially forming a conductive material...
US-9,318,380 Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure...
A semiconductor device has a first conductive layer formed over a first substrate. A second conductive layer is formed over a second substrate. A first...
US-9,318,379 Methods of manufacturing semiconductor devices including air gap spacers
A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of...
US-9,318,378 Slot designs in wide metal lines
A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising:...
US-9,318,377 Etch damage and ESL free dual damascene metal interconnect
A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias...
US-9,318,376 Through substrate via with diffused conductive component
A front-end-of-line through-substrate via is provided for application in certain semiconductor device fabrication, including microelectromechanical (MEMS)...
US-9,318,375 Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming...
US-9,318,374 Semiconductor storage device comprising peripheral circuit, Shielding layer, and memory cell array
Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array...
US-9,318,373 Method and apparatus for protection against process-induced charging
A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one...
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