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Patent # Description
US-9,318,372 Method of stressing a semiconductor layer
One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor...
US-9,318,371 Shallow trench isolation structure
A semiconductor device includes a semiconductor substrate, an active region and a trench isolation. The active region is formed in the semiconductor substrate....
US-9,318,370 High-k dielectric liners in shallow trench isolations
A circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor...
US-9,318,369 Patterns of a semiconductor device and method of manufacturing the same
A semiconductor device including a plurality of active patterns, a plurality of first isolation layer patterns and a plurality of second isolation layer...
US-9,318,368 Photomask and method for forming dual STI structure by using the same
In a method for manufacturing a dual shallow trench isolation structure, a substrate is provided, and a mask layer is formed on the substrate. The mask layer is...
US-9,318,367 FinFET structure with different fin heights and method for forming the same
A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins protruding over a substrate, wherein two adjacent first...
US-9,318,366 Method of forming integrated circuit having modified isolation structure
A method includes forming an isolation structure partially buried in a substrate. A portion of the isolation structure protrudes from an upper surface of the...
US-9,318,365 Substrate processing apparatus
A substrate processing apparatus for processing a substrate comprises: a plurality of chuck pins each having an accommodating groove for accommodating a portion...
US-9,318,364 Semiconductor device metallization systems and methods
Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a...
US-9,318,363 Substrate processing system and substrate position correction method
In STEP 1, a mapping operation is carried out by a mapping device. In STEP 2, based on position information for the wafer (W) detected by the mapping operation,...
US-9,318,362 Die bonder and a method of cleaning a bond collet
A die bonder comprises a movable bond collet for holding an electronic device, and a platform which comprises a cleaning surface for cleaning the bond collet...
US-9,318,361 Collet cleaning method and die bonder using the same
An object of the present invention is to provide a collet cleaning method and a die bonder using the same in which a collet can be cleaned without adding a new...
US-9,318,360 Linear high packing density for LED arrays
Apparatus for providing energy to a process chamber are provided herein. In one embodiment, the apparatus include a supporting substrate, a first plurality of...
US-9,318,359 Apparatus for substrate treatment and heating apparatus
The present invention relates to an apparatus for heat-treating a substrate, and more particularly to an apparatus for substrate treatment to perform a heat...
US-9,318,358 Etching device and a method for etching a material of a workpiece
An etching device is provided, the etching device including a process chamber including an etchant, a structure configured to provide a laminar flow of the...
US-9,318,357 Method for producing a multiplicity of optoelectronic semiconductor components
Optoelectronic semiconductor devices and methods for producing optoelectronic semiconductor devices are disclosed. In an embodiment the method includes applying...
US-9,318,356 Substrate strip
Disclosed herein is a substrate strip including: a substrate region having a plurality of substrate units formed therein; a dummy region enclosing the substrate...
US-9,318,355 Power semiconductor device with a double metal contact
A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the...
US-9,318,354 Semiconductor package and fabrication method thereof
A semiconductor package is disclosed, which includes: a substrate having a plurality of switching pads, a plurality of first conductive pads and a plurality of...
US-9,318,353 Method of manufacturing connection structure
A method of manufacturing a connection structure which includes a wiring substrate, a first electronic component that is flip-chip mounted on the front surface...
US-9,318,352 Power module package and method for manufacturing the same
Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes first and second lead frames disposed to...
US-9,318,351 Wiring substrate
A wiring substrate includes a substrate body, a through hole extending through the substrate body from an upper surface to a lower surface of the substrate...
US-9,318,350 Method and apparatus for converting commerical off-the-shelf (COTS) thin small-outline package (TSOP)...
An embodiment of the invention generally relates to a method of converting a commercial off-the-shelf electrical lead to a rugged off-the-shelf electrical lead...
US-9,318,349 Plasma chamber top piece assembly
A plasma processing system for processing a substrate is described. The plasma processing system includes a bottom piece including a chuck configured for...
US-9,318,348 Fabrication of graphene electrodes on diamond substrate
One or more graphene layers may be formed on a diamond substrate by reforming sp.sup.3 hybrid orbitals of C--C bonds in a portion of the diamond substrate into...
US-9,318,347 Wafer backside particle mitigation
A method of particle mitigation which includes obtaining a semiconductor wafer having a nonfunctional backside and a functional frontside on which semiconductor...
US-9,318,346 CMP polishing liquid and polishing method
The CMP polishing liquid containing a medium and silica particles as an abrasive grain dispersed into the medium. The silica particles have a silanol group...
US-9,318,345 Enhancing transistor performance by reducing exposure to oxygen plasma in a dual stress liner approach
When forming strain-inducing dielectric material layers above transistors of different conductivity type, the patterning of at least one strain-inducing...
US-9,318,344 CMOS structures and methods for improving yield
A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner,...
US-9,318,343 Method to improve etch selectivity during silicon nitride spacer etch
Techniques herein include methods to increase etching selectivity among materials. Techniques herein include a cyclical process of etching and oxidation of a...
US-9,318,342 Methods of removing fins for finfet semiconductor devices
One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a...
US-9,318,341 Methods for etching a substrate
Methods for etching a substrate in a plasma etch reactor may include (a) depositing polymer on surfaces of a feature formed in substrate disposed in the etch...
US-9,318,340 Method of manufacturing a semiconductor device
A method of manufacturing a semiconductor device including a wafer using a plasma etching device which includes a chamber, a chuck provided in the chamber to...
US-9,318,339 Polishing slurry and polishing method
The present invention provides a polishing slurry capable of polishing even high-hardness materials such as silicon carbide and gallium nitride at a high...
US-9,318,338 Method for fabricating semiconductor device
A method for fabricating a semiconductor device is provided. The method includes the following steps. Firstly, a substrate having a nitride layer and a platinum...
US-9,318,337 Three dimensional three semiconductor high-voltage capacitors
An integrated circuit capacitor. The capacitor includes a substrate, a first conductor, and a first insulating region between the first conductor and the...
US-9,318,336 Non-volatile memory structure employing high-k gate dielectric and metal gate
A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory...
US-9,318,335 Method for fabricating semiconductor device including nitrided gate insulator
A method of fabricating a semiconductor device includes forming an interface layer on a substrate, forming a first gate insulating layer having a first...
US-9,318,334 Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region...
US-9,318,333 Dielectric extension to mitigate short channel effects
In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed....
US-9,318,332 Grid for plasma ion implant
A grid for minimizing effects of ion divergence in plasma ion implant. The plasma grid is made of a flat plate having a plurality of holes, wherein the holes...
US-9,318,331 Method and system for diffusion and implantation in gallium nitride based devices
A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined...
US-9,318,330 Patterning process method for semiconductor devices
A method for forming a semiconductor device that includes a SiARC layer formed over a photoresist film which is formed over spacer portions which are formed on...
US-9,318,329 Methods of forming vertical cell semiconductor devices with single-crystalline channel structures
Methods of fabricating a vertical cell semiconductor device including forming a hole passing through a stacked structure of alternating insulating and...
US-9,318,328 Method and apparatus for forming silicon film
A method of forming a silicon film includes a first film forming process, an etching process, a doping process, and a second film forming process. In the first...
US-9,318,327 Semiconductor devices having low threading dislocations and improved light extraction and methods of making the...
Semiconductor device structures are provided that are suitable for use in the fabrication of electronic devices such as light emitting diodes. The semiconductor...
US-9,318,326 Dislocation and stress management by mask-less processes using substrate patterning and methods for device...
Structures and methods for producing active layer stacks of lattice matched, lattice mismatched and thermally mismatched semiconductor materials, with low...
US-9,318,325 Defect reduction using aspect ratio trapping
Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations...
US-9,318,324 Manufacturing method of SiC epitaxial substrate, manufacturing method of semiconductor device, and...
A manufacturing method of an SiC epitaxial substrate of an embodiment includes performing a first and a second process alternately to form an n type SiC layer,...
US-9,318,323 Semiconductor devices with graphene nanoribbons
Semiconductor devices with graphene nanoribbons and methods of manufacture are disclosed. The method includes forming at least one layer of Si material on a...
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