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Patent # Description
US-9,324,830 Self-aligned contact process enabled by low temperature
Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal...
US-9,324,829 Method of forming a trench electrode device with wider and narrower regions
A method includes forming a trench extending from a first surface of a semiconductor body into the semiconductor body such that a first trench section and at...
US-9,324,828 Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure, and methods of forming
Various particular embodiments include a method of amorphizing a portion of silicon underneath the N+ base section of a PNP transistor structure. After...
US-9,324,827 Non-planar schottky diode and method of fabrication
A non-planar Schottky diode includes a semiconductor substrate of a first type, the first type including one of n-type and p-type. The structure further...
US-9,324,826 Semiconductor device and manufacturing method of the same
A semiconductor device of an embodiment at least includes: a SiC substrate; and a gate insulating film formed on the SiC substrate, wherein at an interface...
US-9,324,825 Manufacturing method of a graphene-based electrochemical sensor, and electrochemical sensor
A manufacturing method of an electrochemical sensor comprises forming a graphene layer on a donor substrate, laminating a film of dry photoresist on the...
US-9,324,824 Transistor, semiconductor device and method of manufacturing the same
A semiconductor device including a central region, side regions located in both sides of the central region, and conductive layers including a first barrier...
US-9,324,823 Semiconductor device having a tapered gate structure and method
A semiconductor device includes a semiconductor body having a first surface vertically spaced apart from a second surface. A first trench vertically extends...
US-9,324,822 Gate dielectric protection for transistors
At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive...
US-9,324,821 Compound semiconductor device and manufacturing method of the same
An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and...
US-9,324,820 Method for forming semiconductor structure with metallic layer over source/drain structure
A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a source/drain...
US-9,324,819 Semiconductor device
A semiconductor device includes an active layer, source electrodes, drain electrodes, gate electrodes, a first dielectric layer, source trace, first source...
US-9,324,818 Gate-all-around semiconductor device and method of fabricating the same
The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating...
US-9,324,817 Method for forming a transistor device having a field electrode
A method for forming a transistor device includes forming a field electrode arrangement by forming a trench in a first surface of a semiconductor body, forming...
US-9,324,816 Semiconductor device
According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer provided in a portion on the first...
US-9,324,815 Semiconductor device
According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first...
US-9,324,814 Silicon carbide single-crystal substrate
A silicon carbide single-crystal substrate includes a first surface, a second surface opposite to the first surface, and a peripheral edge portion sandwiched...
US-9,324,813 Doped zinc oxide as N.sup.+ layer for semiconductor devices
A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type layer is formed on or in the...
US-9,324,812 Semiconductor device including nanowire transistor
A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel...
US-9,324,811 Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same
Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are...
US-9,324,810 Semiconductor device including oxide semiconductor film
A highly reliable semiconductor device having stable electrical characteristics is provided. Oxide films each containing one or more kinds of metal elements...
US-9,324,809 Method and system for interleaved boost converter with co-packaged gallium nitride power devices
An electronic package includes a leadframe and a plurality of pins. The electronic package also includes a first gallium nitride (GaN) transistor comprising a...
US-9,324,808 Semiconductor device, power-supply unit, amplifier and method of manufacturing semiconductor device
A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed...
US-9,324,807 Silicon carbide MOSFET with integrated MOS diode
A monolithically integrated MOS channel in gate-source shorted mode is used as a diode for the third quadrant conduction path for a power MOSFET. The MOS diode...
US-9,324,806 Silicon carbide semiconductor device
A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer of a first conductivity type; a field insulating film formed on a surface...
US-9,324,805 Flexible graphene switching device
Provided is a graphene switching device including: a graphene layer formed on a substrate; a plurality of semiconductor nanowires on the substrate; a first...
US-9,324,804 Graphene-on-semiconductor substrates for analog electronics
Electrically conductive material structures, analog electronic devices incorporating the structures and methods for making the structures are provided. The...
US-9,324,803 Superjunction power device and manufacturing method
A method for manufacturing a semiconductor power device, comprising the steps of: forming a trench in a semiconductor body having a first type of conductivity;...
US-9,324,802 Spacer supported lateral channel FET
A semiconductor device includes a semiconductor material and trenches extending into the semiconductor material from a first main surface of the semiconductor...
US-9,324,801 Nanowire FET with tensile channel stressor
Fin stacks including a silicon germanium alloy portion and a silicon portion are formed on a surface of a substrate. Sacrificial gate structures are then formed...
US-9,324,800 Bidirectional MOSFET with suppressed bipolar snapback and method of manufacture
A bidirectional trench FET device includes a semiconductor substrate, a trench in the substrate extending vertically from the surface of the substrate, and a...
US-9,324,799 FinFET structures having uniform channel size and methods of fabrication
Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first...
US-9,324,798 Semiconductor device and method for manufacturing the same
In one embodiment, a semiconductor device includes a first diffusion layer of a first conductive type and a second diffusion layer of a second conductive type...
US-9,324,797 Gate-all-around nanowire MOSFET and method of formation
A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a...
US-9,324,796 Gate-all-around nanowire MOSFET and method of formation
A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a...
US-9,324,795 Gate-all-around nanowire MOSFET and method of formation
A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a...
US-9,324,794 Self-formation of high-density arrays of nanostructures
A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a...
US-9,324,793 Method for controlling the profile of an etched metallic layer
An ashing chemistry employing a combination of Cl.sub.2 and N.sub.2 is provided, which removes residual material from sidewalls of a patterned metallic hard...
US-9,324,792 FinFET including varied fin height
According to another embodiment, a semiconductor finFET device includes a semiconductor substrate. The finFET device further includes at least one first...
US-9,324,791 Semiconductor element
A semiconductor element includes a substrate and a semiconductor layer. The substrate has a first main face and a second main face. The semiconductor layer is...
US-9,324,790 Self-aligned dual-height isolation for bulk FinFET
A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group...
US-9,324,789 Memory device and method for fabricating the same
The memory device is provided to include a substrate, a plurality of stack structures, conductive pillars, charge storage layers, and third conductive layers....
US-9,324,788 Semiconductor device
In a semiconductor device, a lightly doped second semiconductor layer of a first conductive type is joined with a heavily doped first semiconductor layer of the...
US-9,324,787 Semiconductor device
According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, and a...
US-9,324,786 Semiconductor device and method for fabricating the same
A semiconductor device includes a semiconductor layer, a plurality of first doped regions, a gate structure, and second and third doped regions. The...
US-9,324,785 Semiconductor device and method for fabricating the same
A semiconductor device includes: a plurality of stacked semiconductor layers; a plurality of composite doped regions separately and parallelly disposed in a...
US-9,324,784 Electronic device having a termination region including an insulating region
An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination...
US-9,324,783 Soft switching semiconductor device and method for producing thereof
A semiconductor device has a semiconductor body with a first side and a second side that is arranged distant from the first side in a first vertical direction....
US-9,324,782 Semiconductor device
A semiconductor layer, a well region, and a source region form a unit cell. The unit cell is defined into a certain shape in plan view at a main surface of the...
US-9,324,781 Semiconductor devices and methods of fabricating the same
Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage...
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