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Patent # Description
US-9,324,730 Vertical memory devices and methods of manufacturing the same
A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of...
US-9,324,729 Non-volatile memory device having a multilayer block insulating film to suppress gate leakage current
According to one embodiment, a non-volatile memory device includes electrodes, one semiconductor layer, conductive layers, and first and second insulating...
US-9,324,728 Three-dimensional vertical gate NAND flash memory including dual-polarity source pads
A memory includes a three-dimensional array including a plurality of levels is described. Each level includes a bit line pad, a source line pad, and a plurality...
US-9,324,727 Memory devices having semiconductor patterns on a substrate and methods of manufacturing the same
A memory device may include a plurality of semiconductor patterns on a substrate including a plurality of first impurity regions doped at a first impurity...
US-9,324,726 Method for manufacturing a semiconductor device
The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode...
US-9,324,725 Semiconductor device and a manufacturing method thereof
The performances of a semiconductor device are improved. The semiconductor device has a first control gate electrode and a second control gate electrode spaced...
US-9,324,724 Method of fabricating a memory structure
The present invention provides a method of fabricating a memory structure, especially forming an oxide on top of a spacer to prevent the spacer from being...
US-9,324,723 Semiconductor integrated circuit device and a method of manufacturing the same
A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first...
US-9,324,722 Utilization of block-mask and cut-mask for forming metal routing in an IC device
A method of forming metal routing in an IC device utilizing a cut mask in conjunction with a block mask is disclosed. Embodiments include forming a hard-mask...
US-9,324,721 Pitch-halving integrated circuit process
A pitch-halving IC process is described. Parallel base line patterns are formed over a substrate, each being connected with a hammerhead pattern at a first or...
US-9,324,720 Meander line resistor structure
A method comprises implanting ions in a substrate to form a first active region and a second active region, depositing a first dielectric layer over the...
US-9,324,718 Three dimensional multilayer circuit
A three dimensional multilayer circuit (600) includes a plurality of crossbar arrays (512) made up of intersecting crossbar segments (410, 420) and programmable...
US-9,324,717 High mobility transistors
An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have...
US-9,324,716 Semiconductor device and fabricating method thereof
A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work...
US-9,324,715 Flip-flop layout architecture implementation for semiconductor device
A semiconductor device includes a substrate including PMOSFET and NMOSFET regions. First and second gate electrodes are provided on the PMOSFET region, and...
US-9,324,714 Semiconductor device
In one embodiment, a semiconductor device includes a semiconductor substrate, and first and second transistors of first and second conductivity types on the...
US-9,324,713 Eliminating field oxide loss prior to FinFET source/drain epitaxial growth
Method for forming FinFET source/drain regions with reduced field oxide loss and the resulting devices are disclosed. Embodiments include forming silicon fins...
US-9,324,712 Integrated circuit and related manufacturing method
A method for manufacturing an integrated circuit may include the following steps: forming a first transistor, which includes a first active region; forming a...
US-9,324,711 Semiconductor device and method of manufacturing semiconductor device
A first transistor includes a first impurity layer of a first conduction type formed in a first region of a semiconductor substrate, a first epitaxial...
US-9,324,710 Very planar gate cut post replacement gate process
A semiconductor structure with improved gate planarity and method of fabrication are provided. In a replacement gate scheme, an array of sacrificial gate...
US-9,324,709 Self-aligned gate contact structure
Embodiments of present invention provide a method of forming a semiconductor device. The method includes depositing a layer of metal over one or more channel...
US-9,324,708 Power semiconductor device
An exemplary power semiconductor device with a wafer having an emitter electrode on an emitter side and a collector electrode on a collector side, an (n-) doped...
US-9,324,707 Integrated circuits and methods of design and manufacture thereof
Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a...
US-9,324,706 Method of making an integrated switchable capacitive device
A method is provided for forming an integrated circuit chip with a variable capacitor disposed in a metallization. A back end of line metallization is formed...
US-9,324,705 Lateral bipolar junction transistor
A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the...
US-9,324,704 Electronic device, circuit and method for trimming electronic components
A circuit comprises a plurality of electronic components integrated on a substrate, and a trim arrangement arranged to provide trim data to a respective...
US-9,324,703 High-performance device for protection from electrostatic discharge
The semiconductor device for protection from electrostatic discharges comprises several modules (MDi) for protection from electrostatic discharges comprising...
US-9,324,702 Photoelectric device
A photoelectric device includes a base, an LED (light emitting diode) element and a zener diode. The base includes a first electrode and a second electrode. The...
US-9,324,701 Diode circuit layout topology with reduced lateral parasitic bipolar action
Diode circuit layout topologies and methods are disclosed that exhibit reduced lateral parasitic bipolar characteristics at lateral parasitic bipolar circuit...
US-9,324,700 Semiconductor device and method of forming shielding layer over integrated passive device using conductive channels
A semiconductor device is made by providing a substrate, forming a first insulation layer over the substrate, forming a first conductive layer over the first...
US-9,324,699 Semiconductor device
The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an...
US-9,324,698 Multi-chip structure and method of forming same
A device comprises a first chip and a second chip stacked together to form a multi-chip structure, wherein the multi-chip structure is embedded in an...
US-9,324,697 Chip-on-heatsink light emitting diode package and fabrication method
The present disclosure provides a novel light-emitting diode package and corresponding fabrication method for making such a package. The novel LED package...
US-9,324,696 Package-on-package devices, methods of fabricating the same, and semiconductor packages
In a package-on-package (PoP) device according to the inventive concepts, an anisotropic conductive film is disposed between a lower semiconductor package and...
US-9,324,695 Method of tuning color temperature of light-emitting device
A method of tuning color temperature of light-emitting device having an overall color temperature, comprising: providing a carrier; disposing at least two LED...
US-9,324,694 Light-emitting diode
A light-emitting diode (LED) is provided. An LED die includes a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a first...
US-9,324,693 Folded 3-D light sheets containing printed LEDs
A method of forming a light sheet includes printing a layer of inorganic LEDs on a first conductive surface of a substrate, depositing a first dielectric layer,...
US-9,324,692 Transparent LED layer between phosphor layer and light exit surface of lamp
A flexible light sheet lamp includes a thin substrate and an array of printed microscopic vertical LEDs (VLEDs) sandwiched between a transparent first conductor...
US-9,324,691 Optoelectronic device
An optoelectronic device comprising: a substrate; a plurality of semiconductor units electrically connected with each other and disposed jointly on the...
US-9,324,690 Signal delivery in stacked device
Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a...
US-9,324,689 Chip-on-film (COF) tape and corresponding COF bonding method
The present invention provides a chip-on-film (COF) tape and a corresponding COF bonding method. The COF tape comprises a base tape, a plurality of first COFs...
US-9,324,688 Embedded packages having a connection joint group
An embedded package includes a first semiconductor chip embedded in a package substrate, a second semiconductor chip disposed over a first surface of the...
US-9,324,687 Wafer-level passive device integration
A device and fabrication techniques are described that employ wafer-level packaging techniques to fabricate semiconductor devices that include an embedded...
US-9,324,686 Semiconductor chips having improved solidity, semiconductor packages including the same and methods of...
Semiconductor chips are provided. The semiconductor chip includes a semiconductor chip body having an arch-shaped groove in a backside thereof and a...
US-9,324,685 Semiconductor device and method of manufacturing the same
There is provided a semiconductor device having a converter circuit, a brake circuit and an inverter circuit and manufacturable by a simplified manufacturing...
US-9,324,684 Semiconductor device and manufacturing method thereof
A manufacturing method of a semiconductor device according to the present invention includes the steps of (a) preparing an insulating or conductive substrate;...
US-9,324,683 Semiconductor package and method of manufacturing the same
In one embodiment, a semiconductor package includes a circuit substrate, a plurality of semiconductor chips stacked on the circuit substrate, insulating...
US-9,324,682 Method and system for height registration during chip bonding
A method of fabricating a composite semiconductor structure is provided. Pedestals are formed in a recess of a first substrate. A second substrate is then...
US-9,324,681 Pin attachment
A method for making a microelectronic package includes the steps of providing a microelectronic assembly that further includes a substrate with a plurality of...
US-9,324,680 Solder attach apparatus and method
An electronic device including a solder structure and methods of forming an electrical interconnection are shown. Solder structures are shown including a solder...
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