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Patent # Description
US-9,324,679 Two-shaft drive mechanism and die bonder
A two-shaft drive mechanism includes a processing unit, a first linear motor provided with a first movable portion and a first fixed portion, which elevates the...
US-9,324,678 Low profile zero/low insertion force package top side flex cable connector architecture
An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a...
US-9,324,677 Semiconductor device and method for manufacturing semiconductor device
A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the...
US-9,324,676 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods of manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a method of...
US-9,324,675 Structures for reducing corrosion in wire bonds
A semiconductor structure includes a bond pad and a wire bond coupled to the bond pad. The wire bond includes a bond in contact with the bond pad. The wire bond...
US-9,324,674 Die substrate assembly and method
A die comprising a body of semiconductor material, said body configured to receive a solder layer of gold containing alloy for use in die bonding said die to a...
US-9,324,673 Integrated circuit packaging system with wafer level reconfiguration and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: removing a portion of a leadframe to form a partially removed region and an upper...
US-9,324,672 Semiconductor device and method of forming dual-active sided semiconductor die in fan-out wafer level chip...
In a semiconductor device, a plurality of conductive pillars is formed over a temporary carrier. A dual-active sided semiconductor die is mounted over the...
US-9,324,671 Metal pillar bump packaging strctures and fabrication methods thereof
A method for fabrication a metal pillar bump packaging structure is provided. The method includes providing a semiconductor substrate; and forming a metal...
US-9,324,670 Semiconductor device with copper-tin compound on copper connector
An embodiment is a method for forming a semiconductor assembly including cleaning a connector including copper formed on a substrate, applying cold tin to the...
US-9,324,669 Use of electrolytic plating to control solder wetting
A method including forming a copper pillar, electroplating a metal layer on a top surface and a sidewall of the copper pillar, and electroplating a metal cap...
US-9,324,668 Bonding structures and methods of forming the same
A package includes a package component and a second package component. A first elongated bond pad is at a surface of the first package component, wherein the...
US-9,324,667 Semiconductor devices with compliant interconnects
A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the...
US-9,324,666 Electronic device and electronic apparatus
The present invention relates to electronic technology and discloses an electronic device and an electronic apparatus, capable of solving the problem that an...
US-9,324,665 Metal fuse by topology
Embodiments of the present disclosure describe techniques and configurations for overcurrent fuses in integrated circuit (IC) devices. In one embodiment, a...
US-9,324,664 Embedded chip package structure
An embedded chip package structure including a core layer, a chip, a first circuit layer and a second circuit layer is provided. The core layer includes a first...
US-9,324,663 Semiconductor device including a plurality of magnetic shields
A semiconductor device includes a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, a side surface...
US-9,324,662 Semiconductor device and manufacturing method thereof for protecting metal-gate from oxidation
A semiconductor device and a manufacturing method thereof is provided. The method comprises: providing a substrate for the semiconductor device with a gate...
US-9,324,661 Semiconductor package and method of manufacturing the same
An aligning guide, a semiconductor package comprising an aligning guide, and a method of manufacturing a semiconductor package comprising an aligning guide are...
US-9,324,660 Device and method for alignment of vertically stacked wafers and die
A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern...
US-9,324,659 Semiconductor device and method of forming POP with stacked semiconductor die and bumps formed directly on the...
A semiconductor device has a first semiconductor wafer mounted to a carrier. A second semiconductor wafer is mounted to the first semiconductor wafer. The first...
US-9,324,658 High speed, high density, low power die interconnect system
A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include...
US-9,324,657 Semiconductor package and method of fabricating the same
Provided are semiconductor packages and methods of fabricating the same. The method may include, stacking a lower semiconductor chip on a lower package...
US-9,324,656 Methods of forming contacts on semiconductor devices and the resulting devices
One method of forming a transistor device comprised of a source/drain region and a gate structure includes forming a dielectric layer above the gate structure...
US-9,324,655 Modified via bottom for beol via efuse
An electronic fuse structure including an M.sub.x level including a first M.sub.x metal, a second M.sub.x metal, and an M.sub.x cap dielectric above of the...
US-9,324,654 Integrated circuits with electronic fuse structures
Integrated circuits including electronic fuse structures are disclosed. In some examples, the electronic fuse structure includes a fuse part and first and...
US-9,324,653 Semiconductor device
On a single semiconductor package PK1, m semiconductor chips CP1 to CPm are mounted, and the semiconductor package PK1 has external terminals T shared by m pad...
US-9,324,652 Method of creating a maskless air gap in back end interconnections with double self-aligned vias
A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending...
US-9,324,651 Package structure
A package structure includes a chip, a substrate, wires and a molding compound. The chip includes an active surface, a back surface and bonding pads disposed on...
US-9,324,650 Interconnect structures with fully aligned vias
A method of forming a fully aligned via connecting two metal lines on different Mx levels by forming a recessed opening above a first metal line in a first ILD;...
US-9,324,649 Semiconductor device including a cap substrate on a side wall that is disposed on a semiconductor substrate
Certain embodiments provide a semiconductor device including a semiconductor substrate, a side wall portion, a cap substrate, a plurality of external connection...
US-9,324,648 Semiconductor device, method for manufacturing same, and electronic component
A plurality of insulating film rings are selectively formed on a front surface of an Si substrate, and surface pads are formed opposite openings of the...
US-9,324,647 Circuit module and method of manufacturing the same
Manufacturing method and circuit module, which comprises an insulator layer and, inside the insulator layer, at least one component, which comprises contact...
US-9,324,646 Open source power quad flat no-lead (PQFN) package
According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase, V-phase, and W-phase power switches situated on the PQFN...
US-9,324,645 Method and system for co-packaging vertical gallium nitride power devices
An electronic package includes a leadframe and a plurality of pins. The electronic package also includes a first gallium nitride (GaN) transistor comprising a...
US-9,324,644 Semiconductor device
A trench portion (trench or groove) is formed at each of four corner portions of a chip bonding region having a quadrangular planar shape smaller than an...
US-9,324,643 Integrated circuit device having exposed contact pads and leads supporting the integrated circuit die and...
An integrated circuit (IC) device includes an IC die and encapsulation material surrounding the IC die. A first set of leads is coupled to the IC die and has...
US-9,324,642 Method of electrically isolating shared leads of a lead frame strip
A lead frame strip includes a plurality of connected unit lead frames, each unit lead frame having a die paddle and a plurality of leads connected to a...
US-9,324,641 Integrated circuit packaging system with external interconnect and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: providing a routable distribution layer on a leadframe; mounting an integrated...
US-9,324,640 Triple stack semiconductor package
A method for forming a stacked semiconductor package includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality...
US-9,324,639 Electronic device comprising an improved lead frame
An electronic device includes a chip and a support element which supports the chip. Leads are provided to be electrically coupled to at least one terminal of...
US-9,324,638 Compact wirebonded power quad flat no-lead (PQFN) package
Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical ...
US-9,324,637 Quad flat non-leaded semiconductor package with wettable flank
A Quad Flat Non-leaded (QFN) semiconductor package has a semiconductor die mounted on a die flag of a lead frame. A molded housing with a base and sides covers...
US-9,324,636 Resin-sealed semiconductor device and associated wiring and support structure
A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of...
US-9,324,635 Semiconductor interconnect structure having a graphene-based barrier metal layer
An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based...
US-9,324,634 Semiconductor interconnect structure having a graphene-based barrier metal layer
An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based...
US-9,324,633 Multi-level package assembly having conductive vias coupled to chip carrier for each level and method for...
A package assembly and a method for manufacturing the same are disclosed. The package assembly includes semiconductor chips, encapsulant layers, and a chip...
US-9,324,632 Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method
A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI...
US-9,324,631 Semiconductor device including a stress buffer material formed above a low-k metallization system
A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may...
US-9,324,630 Semiconductor device
A cooling fin 9 is joined to a semiconductor element 1. A resin 10 encapsulates the semiconductor element 1. A portion of the cooling fin 9 projects from a...
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