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| Patent # | Description |
|---|---|
| US-9,324,629 |
Tooling for coupling multiple electronic chips A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding... |
| US-9,324,628 |
Integrated circuit heat dissipation using nanostructures An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature... |
| US-9,324,627 |
Electronic assembly for mounting on electronic board An embodiment of an electronic assembly for mounting on an electronic board includes a plurality of electric contact regions exposed on a mounting surface of... |
| US-9,324,626 |
Interposers with circuit modules encapsulated by moldable material in a
cavity, and methods of fabrication Stacked dies (110) are encapsulated in an interposer's cavity (304) by multiple encapsulant layers (524) formed of moldable material. Conductive paths (520,... |
| US-9,324,625 |
Gated diode, battery charging assembly and generator assembly A gated diode may include source zones and a drain zone which are both of a first conductivity type. The source zones directly adjoin a first surface of a... |
| US-9,324,624 |
Optimizing light extraction efficiency for an LED wafer The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED... |
| US-9,324,623 |
Method of manufacturing semiconductor device having active fins Provided is a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor includes preparing a substrate on which a first... |
| US-9,324,622 |
Semiconductor device and method of forming the same A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of... |
| US-9,324,621 |
Providing shallow trench isolation structures through a backside of a
metal-oxide semiconductor device Embodiments of the present disclosure provide a method of making a metal-oxide semiconductor (MOS) device. The method comprises providing an apparatus that... |
| US-9,324,620 |
Metal gate structure and method of making the same A metal gate structure includes a substrate including a dense region and an iso region. A first metal gate structure is disposed within the dense region, and a... |
| US-9,324,619 |
Semiconductor device and method of fabricating the same A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming... |
| US-9,324,618 |
Methods of forming replacement fins for a FinFET device One illustrative method includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a substrate fin, forming a... |
| US-9,324,617 |
Methods of forming elastically relaxed SiGe virtual substrates on bulk
silicon One method disclosed herein includes forming a virtual substrate by forming a sacrificial semiconductor material in a trench between a plurality of silicon fin... |
| US-9,324,616 |
Method of manufacturing flip-chip type semiconductor device An object of the present invention is to provide a method of manufacturing a flip-chip type semiconductor device with a simplified process, in which various... |
| US-9,324,615 |
Method for producing a semiconductor body A method of producing a semiconductor body includes providing a semiconductor wafer having at least two chip regions and at least one separating region arranged... |
| US-9,324,614 |
Through via nub reveal method and structure A method includes applying a backside passivation layer to an inactive surface of an electronic component and to enclose a through via nub protruding from the... |
| US-9,324,613 |
Method for forming through substrate vias with tethers A method for forming through silicon vias (TSVs) in a silicon substrate is disclosed. The method involves forming a silicon post as an substantially continuous... |
| US-9,324,612 |
Shielded coplanar line In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line,... |
| US-9,324,611 |
Corrosion resistant via connections in semiconductor substrates and
methods of making same Devices and methods for protecting the metal within a via in a semiconductor substrate from corrosion are provided. Specifically, embodiments of the present... |
| US-9,324,610 |
Method for fabricating semiconductor device A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a... |
| US-9,324,609 |
Methods of manufacturing semiconductor devices having high aspect ratio Methods of forming a hard mask capable of implementing an electrode having a high aspect ratio are provided. A molding layer may be formed on a substrate. A... |
| US-9,324,608 |
Method for via plating with seed layer Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening... |
| US-9,324,607 |
GaN power device with solderable back metal A method for fabricating a vertical gallium nitride (GaN) power device can include providing a GaN substrate with a top surface and a bottom surface, forming a... |
| US-9,324,606 |
Self-aligned repairing process for barrier layer A self-aligned repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organometallic compound as a... |
| US-9,324,605 |
Method of fabricating a vertically oriented inductor within interconnect
structures and capacitor structure thereof The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a horizontal surface. The... |
| US-9,324,604 |
Gap-fill methods Provided are gap-fill methods. The methods comprise: (a) providing a semiconductor substrate having a relief image on a surface of the substrate, the relief... |
| US-9,324,603 |
Semiconductor structures with shallow trench isolations A method is disclosed that includes the operations outlined below. An insulating material is disposed within a plurality of trenches on a semiconductor... |
| US-9,324,602 |
Substrate inverting apparatus and substrate processing apparatus Provided is a technique which can properly invert a plurality of substrates at a time. To achieve this object, a substrate inverting apparatus includes: a... |
| US-9,324,601 |
Low temperature adhesive resins for wafer bonding A method for adhesive bonding in microelectronic device processing is provided that includes bonding a handling wafer to a front side of a device wafer with an... |
| US-9,324,600 |
Mounting table structure and plasma film forming apparatus A mounting table structure includes a mounting table body, made of a conductive material, for mounting thereon the processing target object and serving as an... |
| US-9,324,599 |
Container opening/closing device The present invention provides a container opening/closing device for opening and closing a lid of a container. The container comprises a container body... |
| US-9,324,598 |
Substrate processing system and method A system for processing substrates has a vacuum enclosure and a processing chamber situated to process wafers in a processing zone inside the vacuum enclosure.... |
| US-9,324,597 |
Vertical inline CVD system The present invention generally relates to a vertical CVD system having a processing chamber that is capable of processing multiple substrates. The multiple... |
| US-9,324,596 |
Substrate storage rack The present disclosure relates to a substrate storage rack, including a hollow rack body with a first, a second, a third, and a fourth lateral surfaces, wherein... |
| US-9,324,595 |
Load port apparatus and method of detecting object to be processed To enable appropriate wafer mapping in the case where a wafer is stored at the highest level, which is provided as a reserve, of a pod, a load port apparatus... |
| US-9,324,594 |
Workpiece handling modules A workpiece handling module including a first housing member and a second housing member pivotally movable relative to the first member forming a housing having... |
| US-9,324,593 |
Wafer processing tape A wafer processing tape includes a release film having a large length; an adhesive layer formed on a first surface of the release film and having a ... |
| US-9,324,592 |
Wafer processing tape A wafer processing tape includes a release film having a large length; an adhesive layer formed on a first surface of the release film and having a ... |
| US-9,324,591 |
Heat treatment apparatus and heat treatment method A heat treatment apparatus including: a processing container for processing wafers held in a boat; heaters for heating the processing container; and a control... |
| US-9,324,590 |
Processing methods and apparatus with temperature distribution control Wafer treatment process and apparatus is provided with a wafer carrier arranged to hold wafers and to inject a fill gas into gaps between the wafers and the... |
| US-9,324,589 |
Multiplexed heater array using AC drive for semiconductor processing A heating plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar heater... |
| US-9,324,588 |
Data analysis method for plasma processing apparatus, plasma processing
method and plasma processing apparatus A stable etching process is realized at an earlier stage by specifying the combination of wavelength and time interval, which exhibits a minimum prediction... |
| US-9,324,587 |
Method for manufacturing semiconductor structure A method includes followings operations. A substrate including a first surface and a second surface is provided. The substrate and a transparent film are heated... |
| US-9,324,586 |
Chip-packaging module for a chip and a method for forming a chip-packaging
module A chip-packaging module for a chip is provided, the chip-packaging module including a chip including a first chip side, wherein the first chip side includes an... |
| US-9,324,585 |
Semiconductor package and method of fabricating the same A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer... |
| US-9,324,584 |
Integrated circuit packaging system with transferable trace lead frame System and method of manufacturing an integrated circuit packaging system using transferable trace lead frame. A lead frame is provided having lower metal... |
| US-9,324,583 |
Packaging method The present invention relates to a packaging method including the steps: a cementing layer is formed on a carrier board; the functional sides of chips and... |
| US-9,324,582 |
Semiconductor package and fabrication method thereof A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an... |
| US-9,324,581 |
Method for manufacturing semiconductor device A wafer is mounted to a dicing frame using a holding tape. A plurality of semiconductor devices are provided on a center portion of a major surface of the... |
| US-9,324,580 |
Process for fabricating a circuit substrate A process for fabricating a circuit substrate is provided. The process includes the following steps. A carrier is provided. A conductive layer and a dielectric... |
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