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Patent # Description
US-9,324,428 Memory device and operation method thereof
An operation method for a memory device is disclosed. An operation state of the memory device is determined. If to be operated in a first operation state, the...
US-9,324,427 Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes: a cell array including MATs (unit cell arrays) arranged in matrix, each of the MATs having memory cells,...
US-9,324,426 Method for improving sensing margin of resistive memory
A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line...
US-9,324,425 Memory device, method of controlling memory device, and memory system
A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to...
US-9,324,424 Memory device and access method
A memory device includes multiple bit lines extending in a first direction, multiple word lines extending in a second direction crossing the first direction,...
US-9,324,423 Apparatuses and methods for bi-directional access of cross-point arrays
The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of...
US-9,324,422 Adaptive resistive device and methods thereof
A system that incorporates teachings of the subject disclosure may include, for example, a device including a nanoelectrode having a gap, and a resistive change...
US-9,324,421 Method and circuit for switching a memristive device
A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the...
US-9,324,420 Method of estimating deterioration state of memory device and related method of wear leveling
A method of estimating a deterioration state of a memory device comprises reading data from selected memory cells connected to a selected wordline of a memory...
US-9,324,419 Multiple pass programming for memory with different program pulse widths
Techniques are provided for programming memory cells while reducing the effects of detrapping which cause a downshift in the threshold voltage distribution....
US-9,324,418 Nonvolatile memory and method for improved programming with reduced verify
A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to...
US-9,324,417 Systems and methods for avoiding read disturbance in a static random-access memory (SRAM)
Systems and methods are provided for reading from a static random-access memory (SRAM). The systems and methods include activating a first bitline connected to...
US-9,324,416 Pseudo dual port memory with dual latch flip-flop
A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to...
US-9,324,415 Clamping circuit for multiple-port memory cell
A circuit includes a memory cell, a first data line, a second data line, and a clamping unit. The memory cell includes a data node, a first pass gate, and a...
US-9,324,414 Selective dual cycle write operation for a self-timed memory
A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second...
US-9,324,413 Write assist circuit, memory device and method
A write assist circuit includes a first switch, a second switch and a bias voltage circuit. The first switch connects a cell supply voltage node of a memory...
US-9,324,412 Memory architecture
A memory circuit includes a memory cell and a data circuit. In a write operation of the memory cell, the data circuit is configured to provide a first write...
US-9,324,411 Multi-die memory device
A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and...
US-9,324,410 Semiconductor memory device having an output buffer controller
A device includes a data output terminal, an output buffer including n first transistors (n is a natural number greater than 1) connected in parallel with the...
US-9,324,409 Method and apparatus for gating a strobe signal from a memory and subsequent tracking of the strobe signal over...
A method, non-transitory computer readable medium and circuit for gating a strobe (DQS) signal are disclosed. The method sends a read command to a memory, sends...
US-9,324,408 Semiconductor devices and semiconductor systems including the same
A semiconductor memory device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a...
US-9,324,407 Semiconductor apparatus capable of preventing refresh error and memory system using the same
A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active...
US-9,324,406 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a memory cell and a control circuit. The memory cell is such that a ferroelectric film is...
US-9,324,405 CMOS analog memories utilizing ferroelectric capacitors
A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a...
US-9,324,404 MRAM sensing with magnetically annealed reference cell
Systems and method for reading/sensing data stored in magnetoresistive random access memory (MRAM) cells using magnetically annealed reference cells. A MRAM...
US-9,324,403 Voltage-controlled magnetic anisotropy (VCMA) switch and magneto-electric memory (MERAM)
Voltage controlled magnetic tunnel junctions and memory devices are described which provide efficient high speed switching of non-volatile magnetic devices at...
US-9,324,402 High density low power GSHE-STT MRAM
Systems and methods are directed to a memory element comprising a hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magnetoresistive random access...
US-9,324,401 Modular magnetoresistive memory
A magnetoresistive memory element is provided with a read module having a first pinned layer with a magnetoresistance that is readable by a read current...
US-9,324,400 Semiconductor memory device and semiconductor memory system
A semiconductor memory device includes a unit memory bank having a plurality of memory cell mats, which shares a local data line, and divided by a row address;...
US-9,324,399 System and method for a level shifting decoder
According to various embodiments described herein, a circuit includes a decode logic circuit, a buffer coupled to the decode logic, a positive level shifter...
US-9,324,398 Apparatuses and methods for targeted refreshing of memory
Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines...
US-9,324,397 Common die for supporting different external memory types with minimal packaging complexity
A configurable die including a logic element configured to communicate a control and address (CA) signal and a data (DQ) signal, and a first generic physical...
US-9,324,396 Semiconductor apparatus and operating method thereof
A sense amplifier control circuit of a semiconductor apparatus includes a driving unit configured to apply a first voltage to a sense amplifier in response to a...
US-9,324,395 Data sensing circuit of semiconductor apparatus
A data sensing circuit of a semiconductor apparatus includes a sensing unit configured to drive a pair of output lines based on a voltage level difference...
US-9,324,394 Strobe signal generation device and memory apparatus using the same
A strobe signal generation device includes an enable signal generating section, a buffering section and a strobe signal driving section. The enable signal...
US-9,324,393 Tracking mechanisms
A tracking circuit in a memory macro includes a data line, a tracking cell electrically coupled with the data line, a logical gate, a feedback transistor, and a...
US-9,324,392 Memory device and method of performing a write operation in a memory device
The present invention provides a technique for performing write operations within a memory device comprising an array of memory cells. Wordline driver circuitry...
US-9,324,391 Dual event command
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit...
US-9,324,390 Semiconductor devices and semiconductor systems including the same
A semiconductor device includes a first data input/output unit storing first internal input data in a first cell block in response to a first shift data strobe...
US-9,324,389 High performance system topology for NAND memory systems
A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the...
US-9,324,388 Allocating memory address space between DIMMs using memory controllers
A memory controller enters a memory mode, allocating memory address space within a pair of dual in line memory modules (DIMMs) such that each DIMM of the pair...
US-9,324,387 Semiconductor memory device with data path option function
A semiconductor memory device may include a memory cell, a bit line connected to the memory cell, a bit line data latch circuit configured to sense-amplify data...
US-9,324,386 Wide common mode range sense amplifier
A device for comparing voltage levels of a pair of input signals is presented. The device may include a pre-amp circuit and a differential amplifier. The...
US-9,324,385 Semiconductor device for generating initialization of information in response to a first clock and outputting...
A semiconductor device includes an initialization information generation unit configured to operate in response to a first clock and generate first...
US-9,324,384 Sense amplifiers and memory devices having the same
In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection...
US-9,324,383 Source line voltage regulation scheme for leakage reduction
An integrated circuit that includes a generator unit connected to one or more pull-up units, one or more pull-up units connected to one or more source lines and...
US-9,324,382 Resistive memory device capable of improving sensing margin of data
A resistive memory device includes a cell block having a plurality of unit memory cells in which a resistive element and a cell select element are connected to...
US-9,324,381 Antifuse OTP memory cell with performance improvement, and manufacturing method and operating method of memory
An OTP memory cell including an antifuse unit and a select transistor is provided. The antifuse unit includes an antifuse layer and an antifuse gate disposed on...
US-9,324,380 Stacked semiconductor apparatus and semiconductor system capable of inputting signals through various paths
A semiconductor apparatus includes a control signal reception portion. The control signal reception portion may set information related to operation of a memory...
US-9,324,379 Mobile terminal and controlling method thereof
A mobile terminal providing a thumbnail enabling overall content of a video to be previewed and a controlling method thereof are disclosed. The mobile terminal...
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