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Patent # Description
US-9,331,121 Method of manufacturing photoelectric conversion apparatus including pixel well contact
A method of manufacturing a photoelectric conversion apparatus which includes a pixel circuit section having a well where a photoelectric conversion element and...
US-9,331,119 Detection apparatus having interlayer insulating layer composed of organic material and covering layer composed...
A detection apparatus includes a plurality of conversion elements, an interlayer insulating layer, and a covering layer. Each of the plurality of conversion...
US-9,331,118 Sensor and method for color photosensor array with shielded, deep-penetration, photodiodes for color detection
A photosensor has a masking layer having an opening over a central photodiode and a first adjacent photodiode, the first adjacent photodiode covered by the...
US-9,331,117 Sensor and lithographic apparatus
A backside illuminated sensor comprising a supporting substrate, a semiconductor layer which comprises a photodiode comprising a region of n-doped semiconductor...
US-9,331,116 Back side illuminated single photon avalanche diode imaging sensor with high short wavelength detection efficiency
A single photon avalanche diode (SPAD) includes an n doped epitaxial layer disposed in a first semiconductor layer. A p doped epitaxial layer is above the n...
US-9,331,115 Image sensor having a gapless microlenses
An image sensor includes a plurality of photosensitive devices arranged in a semiconductor substrate. A planar layer is disposed over the plurality of...
US-9,331,114 Image pickup device and method of manufacturing the same
To prevent deterioration in the sensitivity of a pixel part caused by variation in the distance between a waveguide and a photo diode and by decay of light due...
US-9,331,113 Wide-field lensless fluorescent imaging on a chip
An imaging device uses a fiber optic faceplate (FOF) with a compressive sampling algorithm for the fluorescent imaging of a sample over an large field-of-view...
US-9,331,112 Semiconductor device including an oxide semiconductor layer
A solid-state image sensor which holds a potential for a long time and includes a thin film transistor with stable electrical characteristics is provided. When...
US-9,331,111 Method of refresh operation for flat panel radiation imager
To provide a method of refresh operation for a flat panel radiation imager that makes it possible to carry out a refresh operation in such a way that electric...
US-9,331,110 Semiconductor device, method of manufacturing semiconductor device, and solid-state imaging apparatus
A semiconductor device includes a gate electrode formed on a substrate with a gate insulating layer in between, an insulating layer of property and thickness...
US-9,331,109 Device for monitoring liquid crystal display and method for manufacturing liquid crystal display
A device for monitoring a liquid crystal display includes: a substrate including a display region and a non-display region disposed at an edge of the display...
US-9,331,108 Semiconductor device
A semiconductor device having a high aperture ratio and including a capacitor capable of increasing the charge capacity is provided. A semiconductor device...
US-9,331,107 Pixel structure
A fabrication method of a pixel structure includes the following steps. A first metal layer is patterned to form a source electrode and a drain electrode. A...
US-9,331,106 Pixel structure and fabrication method thereof
A fabrication method of a pixel structure includes the following steps. A first metal layer is patterned to form a source electrode and a drain electrode. A...
US-9,331,105 Array substrate, manufacturing method thereof and display device
The invention discloses an array substrate, a manufacturing method thereof and a display device. The array substrate includes a gate, an active layer, a source...
US-9,331,104 Array substrate for display device
Discussed is an array substrate for a display device, that may include a plurality of cell portions each including a display area and a non-display area except...
US-9,331,103 Liquid crystal display and manufacturing method thereof
A liquid crystal display includes a substrate, a gate line disposed on the substrate and including a bottom gate electrode, a first insulating layer covering...
US-9,331,102 Liquid crystal display
A liquid crystal display includes: a first substrate; a gate line on the first substrate; a gate insulating layer on the gate line; a semiconductor layer on the...
US-9,331,101 Organic light emitting display panel
The present invention relates to an organic light emitting display panel and a method of manufacturing the same. In accordance with an aspect of the present...
US-9,331,100 Display device
A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable display device including the...
US-9,331,099 Substrate for electro-optical apparatus, electro-optical apparatus, and electronic equipment with improved...
An element substrate is provided with a substrate; a pixel electrode; a light shielding layer which is disposed between the substrate and the pixel electrode...
US-9,331,098 Semiconductor-on-insulator integrated circuit with reduced off-state capacitance
An integrated circuit assembly comprises an insulating layer, a semiconductor layer, a handle layer, a metal interconnect layer, and transistors. The insulating...
US-9,331,097 High speed bipolar junction transistor for high voltage applications
High speed bipolar junction transistor switches for high voltage operations. An example switch includes a bipolar junction transistor including a collector...
US-9,331,096 Method and system for hybrid integration of optical communication systems
Methods and systems for hybrid integration of optical communication systems are disclosed and may include receiving continuous wave (CW) optical signals in a...
US-9,331,095 Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors
Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common...
US-9,331,094 Method of selective filling of memory openings
A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes providing an opening having a different...
US-9,331,093 Three dimensional NAND device with silicon germanium heterostructure channel
A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material...
US-9,331,092 Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays
Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure...
US-9,331,091 3D NAND memory with socketed floating gate cells and process therefor
A 3D NAND memory has vertical NAND strings across multiple memory layers above a substrate, with each memory cell of a NAND string residing in a different...
US-9,331,090 Compact three dimensional vertical NAND and method of making thereof
A NAND device has at least a 3.times.3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air...
US-9,331,089 Semiconductor memory device and method of fabricating the same
The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the...
US-9,331,088 Transistor device with gate bottom isolation and method of making thereof
An embodiment relates to a transistor device including a pillar of semiconductor material extending vertically from a bottom portion in contact with an...
US-9,331,087 Method of manufacturing a nonvolatile memory device
A method of manufacturing a nonvolatile memory device comprises forming a gate insulating layer and a first conductive layer over a semiconductor substrate that...
US-9,331,086 Integrated circuit with trimming
An integrated circuit is provided, which comprises at least one first group each having at least one analog unit; and at least one second group each having at...
US-9,331,085 Non-volatile memory with improved sensing window
A semiconductor device may include: a substrate. First and second gate electrode patterns are disposed on first and second fin type active patterns. The first...
US-9,331,084 Method of manufacturing a semiconductor device and adjusting threshold voltages in the same
A method of manufacturing a semiconductor device is provided. The method includes forming a fin structure on a semiconductor substrate and forming a well region...
US-9,331,083 Techniques for providing a semiconductor memory device
Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus...
US-9,331,082 Three-dimensional semiconductor device
A semiconductor device includes a stacked structure having first conductive layers stacked stepwise and first insulating layers interposed between the first...
US-9,331,081 Semiconductor structure and manufacturing method thereof
The present disclosure provides a method of manufacturing a semiconductor structure. The method includes forming a first mask on a substrate; defining a first...
US-9,331,080 Semiconductor device having contact plug and method of forming the same
A semiconductor device includes an N-type fin and a P-type fin on a substrate, a first gate electrode configured to cross the N-type fin and cover a side...
US-9,331,079 Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a plurality of fins on the...
US-9,331,078 Thin film transistor device
According to one embodiment, provided is a thin film transistor device with further improved area efficiency. First contact regions of a first semiconductor...
US-9,331,077 Semiconductor device and manufacturing method of semiconductor device
A semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type...
US-9,331,076 Group III nitride integration with CMOS technology
A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The...
US-9,331,075 Systems and methods for fabricating semiconductor devices at different levels
Systems and methods are provided for fabricating semiconductor device structures on a substrate. For example, a substrate including a first region and a second...
US-9,331,074 Semiconductor device and manufacturing method thereof
A semiconductor device includes first and second Fin FET transistors and a separation plug made of an insulating material and disposed between the first and...
US-9,331,073 Epitaxially grown quantum well finFETs for enhanced pFET performance
A method of forming a quantum well having a conformal epitaxial well on a {100} crystallographic orientated fin. The method may include: forming fins in a {100}...
US-9,331,072 Integrated circuit devices having air-gap spacers defined by conductive patterns and methods of manufacturing...
Integrated circuit devices having a cavity and methods of manufacturing the integrated circuit devices are provided. The integrated circuit devices may include...
US-9,331,071 Semiconductor device and manufacturing method thereof
Provided is an in-wiring-layer active element (component) which allows for electrical isolation between a gate electrode and a channel in a top gate structure....
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